ADUC7023BCBZ62I-R7 datasheet(56/98 Pages) AD

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ADuC7023

Data Sheet

Rev. H | Page 56 of 98

Table 62. GPxCLR MMR Bit Descriptions

Bit

Description

31 to 24

Reserved.

23 to 16

Data port x clear bit.

This bit is set to 1 by the user to clear the bit on Port x;

this bit also clears the corresponding bit in the GPxDAT

MMR.

This bit is cleared to 0 by the user; this bit does not affect

the data out.

15 to 0

Reserved.

SERIAL PERIPHERAL INTERFACE

The ADuC7023 integrates a complete hardware serial

peripheral interface (SPI) on chip. SPI is an industry standard,

synchronous serial interface that allows eight bits of data to be

synchronously transmitted and simultaneously received, that is,

full duplex up to a maximum bit rate of 20 Mbps.

The SPI port can be configured for master or slave operation and

typically consists of four pins: MISO, MOSI, SCLK, and SPISS.

MISO (Master In, Slave Out) Pin

The MISO pin is configured as an input line in master mode

and an output line in slave mode. The MISO line on the master

(data in) should be connected to the MISO line in the slave

device (data out). The data is transferred as byte wide (8-bit)

serial data, MSB first.

MOSI (Master Out, Slave In) Pin

The MOSI pin is configured as an output line in master mode

and an input line in slave mode. The MOSI line on the master

(data out) should be connected to the MOSI line in the slave

device (data in). The data is transferred as byte wide (8-bit)

serial data, MSB first.

SCLK (Serial Clock I/O) Pin

The master serial clock (SCLK) synchronizes the data being

transmitted and received through the MOSI SCLK period.

Therefore, a byte is transmitted/received after eight SCLK

periods. The SCLK pin is configured as an output in master

mode and as an input in slave mode.

In master mode, polarity and phase of the clock are controlled

by the SPICON register, and the bit rate is defined in the

SPIDIV register as follows:

)

(

SPIDIV

UCLK

CLOCK

SERIAL







where:

fUCLK is the clock selected by POWCON1 Bit 7 to Bit 6.

The maximum speed of the SPI clock is independent on the

clock divider bits.

In slave mode, the SPICON register must be configured with

the phase and polarity of the expected input clock. The slave

accepts data from an external master up to 10 Mbps.

In both master and slave modes, data is transmitted on one

edge of the SCLK signal and sampled on the other. Therefore, it

is important that the polarity and phase are configured the

same for the master and slave devices.

SPI Chip Select (SS Input) Pin

In SPI slave mode, a transfer is initiated by the assertion of SS,

which is an active low input signal. The SPI port then transmits

and receives 8-bit data until the transfer is concluded by

deassertion of SS. In slave mode, SS is always an input.

In SPI master mode, the SS is an active low output signal. It

asserts itself automatically at the beginning of a transfer and

deasserts itself upon completion.

Configuring External Pins for SPI Functionality

P1.1 is the slave chip select pin. In slave mode, this pin is an

input and must be driven low by the master. In master mode,

this pin is an output and goes low at the beginning of a transfer

and high at the end of a transfer.

P1.0 is the SCLK pin.

P0.6 is the master in, slave out (MISO) pin.

P0.7 is the master out, slave in (MOSI) pin.

To configure these pins for SPI mode, see the General-Purpose

Input/Output section.

SPI Registers

The following MMR registers control the SPI interface:

SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.

SPI Status Register

Name:

SPISTA

Address:

0xFFFF0A00

Default value:

0x0000

Access:

Read

Function:

This 32-bit MMR contains the status of the SPI

interface in both master and slave modes.

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