ADUC7023BCBZ62I-R7 datasheet(47/98 Pages) AD

47 / 98 page

Data Sheet

ADuC7023

Rev. H | Page 47 of 98

mode only. In 0-to-VREF mode (with VREF < AVDD), the lower

nonlinearity is similar. However, the upper portion of the transfer

function follows the ideal line right to the end (VREF in this case, not

AVDD), showing no signs of endpoint linearity errors.

AVDD

AVDD – 100mV

100mV

0x00000000

0x0FFF0000

Figure 33. Endpoint Nonlinearities Due to Amplifier Saturation

The endpoint nonlinearities conceptually illustrated in Figure 33

get worse as a function of output loading. Most of the ADuC7023

data sheet specifications assume a 5 kΩ resistive load to ground

at the DAC output. As the output is forced to source or sink more

current, the nonlinear regions at the top or bottom of Figure 33

become larger, respectively. With larger current demands, this

can significantly limit output voltage swing.

References to ADC and the DACs

ADC and DACs can be configured to use internal VREF or an

external reference as a reference source. Internal VREF must

work with an external 0.47 μF capacitor. Note that if an external

reference is used, the DACs will no longer meet offset and gain

specifications. If an external reference is required for the ADC,

then the DACs should be configured to use the 0 to AVDD

range.

Table 42. Reference Source Selection for ADC and DAC

REFCON Bit 0

DACxCON[1:0]

Description

ADC works with external

reference. DACs power down.

Reserved.

ADC works with external

reference. DACs work with

internal AVDD.

ADC works with internal

VREF. DACs power down.

ADC and DACs work with an

external reference. The

external reference must be

capable of overdriving the

internal reference.

ADC and DACs work with

internal VREF.

ADC works with internal VREF.

DACs work with internal AVDD.

Configuring DAC Buffers in Op Amp Mode

In op amp mode, the DAC output buffers are used as an op

amp with the DAC itself disabled.

If DACBCFG Bit 0 is set, ADC0 is the positive input to the op

amp, ADC1 is the negative input, and DAC0 is the output. In

this mode, the DAC should be powered down by clearing Bit 0

and Bit 1 of DAC0CON.

If DACBCFG Bit 1 is set, ADC2 is the positive input to the op

amp, ADC3 is the negative input, and DAC1 is the output. In

this mode, the DAC should be powered down by clearing Bit 0

and Bit 1 of DAC1CON.

If DACBCFG Bit 2 is set, ADC4 is the positive input to the op

amp, ADC5 is the negative input, and DAC2 is the output. In

this mode, the DAC should be powered down by clearing Bit 0

and Bit 1 of DAC2CON.

If DACBCFG Bit 3 is set, ADC8 is the positive input to the op

amp, ADC9 is the negative input, and DAC3 is the output. In

this mode, the DAC should be powered down by clearing Bit 0

and Bit 1 of DAC3CON.

DACBCFG Register

Name:

DACBCFG

Address:

0xFFFF0654

Default value:

0x00

Access:

Read/write

Table 43. DACBCFG MMR Bit Designations

Bit

Description

7 to 4

Reserved. Always set to 0.

This bit is set to 1 to configure DAC3 output

buffer in op amp mode.

This bit is cleared for the DAC buffer to

operate as normal.

This bit is set to 1 to configure DAC2 output

buffer in op amp mode.

This bit is cleared for the DAC buffer to

operate as normal.

This bit is set to 1 to configure DAC1 output

buffer in op amp mode.

This bit is cleared for the DAC buffer to

operate as normal.

This bit is set to 1 to configure DAC0 output

buffer in op amp mode.

This bit is cleared for the DAC buffer to

operate as normal.

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