ADUC7023BCBZ62I-R7 datasheet(39/98 Pages) AD

39 / 98 page

Data Sheet

ADuC7023

Rev. H | Page 39 of 98

NONVOLATILE FLASH/EE MEMORY

The ADuC7023 incorporates Flash/EE memory technology on

chip to provide the user with nonvolatile, in-circuit reprogram-

mable memory space.

Like EEPROM, flash memory can be programmed in-system at

a byte level, although it must first be erased. The erase is performed

in page blocks. As a result, flash memory is often and more

correctly referred to as Flash/EE memory.

The Flash/EE memory represents a step closer to the ideal memory

device that includes nonvolatility, in-circuit programmability,

high density, and low cost. Incorporated in the ADuC7023,

Flash/EE memory technology allows the user to update program

code space in-circuit, without needing to replace one-time

programmable (OTP) devices at remote operating nodes.

Each part contains a 64 kB array of Flash/EE memory. The lower

62 kB are available to the user, and the upper 2 kB contain

permanently embedded firmware, allowing in-circuit serial

download. These 2 kB of embedded firmware also contain a

power-on configuration routine that downloads factory-

calibrated coefficients to the various calibrated peripherals

(such as ADC, temperature sensor, and band gap references).

This 2 kB embedded firmware is hidden from user code.

Flash/EE Memory Reliability

The Flash/EE memory arrays on the parts are fully qualified for

two key Flash/EE memory characteristics: Flash/EE memory

cycling endurance and Flash/EE memory data retention.

Endurance quantifies the ability of the Flash/EE memory to be

cycled through many program, read, and erase cycles. A single

endurance cycle is composed of four independent, sequential

events, defined as:

Initial page erase sequence.

Read/verify sequence (single Flash/EE).

Byte program sequence memory.

Second read/verify sequence (endurance cycle).

In reliability qualification, every half word (16-bit wide) location of

the three pages (top, middle, and bottom) in the Flash/EE memory

is cycled 10,000 times from 0x0000 to 0xFFFF. As indicated in

Table 1, the Flash/EE memory endurance qualification is carried

out in accordance with JEDEC Retention Lifetime Specification

A117 over the industrial temperature range of −40° to +125°C.

The results allow the specification of a minimum endurance

figure over a supply temperature of 10,000 cycles.

Retention quantifies the ability of the Flash/EE memory to retain

its programmed data over time. Again, the parts are qualified in

accordance with the formal JEDEC Retention Lifetime Specifi-

cation (A117) at a specific junction temperature (TJ = 85°C). As

part of this qualification procedure, the Flash/EE memory is

cycled to its specified endurance limit before data retention is

characterized. This means that the Flash/EE memory is

guaranteed to retain its data for its fully specified retention

lifetime every time the Flash/EE memory is reprogrammed. In

addition, note that retention lifetime, based on activation

energy of 0.6 eV, derates with TJ as shown in Figure 30.

150

300

450

600

100

125

135

150

JUNCTION TEMPERATURE (°C)

Figure 30. Flash/EE Memory Data Retention

PROGRAMMING

The 62 kB of Flash/EE memory can be programmed in circuit,

using the serial download mode or the provided JTAG mode.

Downloading (In-Circuit Programming) via I2C

The ADuC7023 facilitates code download via the the I2C port.

The parts enter download mode after a reset or power cycle if

the BM pin is pulled low through an external 1 kΩ resistor and

Flash Addess 0x80014 = 0xFFFFFFFF. Once in download

mode, the user can download code to the full 62 kB of Flash/EE

memory while the device is in-circuit in its target application

hardware. An executable PC I2C download is provided as part

of the development system for serial downloading via the I2C. A

USB to I2C download dongle can be purchased from Analog

Devices, Inc. This board connects to the USB port of a PC and

to the I2C port of the ADuC7023. The part number is USB-

I2C/LIN-CONV-Z.

The AN-806 Application Note describes the protocol for serial

downloading via the I2C in more detail.

JTAG Access

The JTAG protocol uses the on-chip JTAG interface to

facilitate code download and debug.

The JTAG interface is active as long as the part is not in download

mode; that is, the P0.0/BM pin = 0 and Address 0x80014 =

0xFFFFFFF at reset.

When debugging, user code must not write to the bits in

GP0CON/GP0DAT corresponding to P0.0/P0.1/P0.2 and P0.3

pins. If user code changes the state of any of these pins, JTAG

debug pods are not able to connect to the ADuC7023. In case

this happens, the user should have a function in code that can

be called externally to mass erase the part. Alternatively, the

user should ensure that Flash Address 0x80014 is erased to

allow erasing of the part through the I2C interface.

ADUC7023BCBZ62I-R7 датащи(PDF) 39 Page - Analog Devices

ADUC7023BCBZ62I-R7 датащи(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

датащи скачать

ссылки URL