ADUC7023BCBZ62I-R7 datasheet(83/98 Pages) AD

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Data Sheet

ADuC7023

Rev. H | Page 83 of 98

IRQCONN Register

The IRQCONN register is the IRQ and FIQ control register.

It contains two active bits. The first to enable nesting and

prioritization of IRQ interrupts and the other to enable

nesting and prioritization of FIQ interrupts.

If these bits are cleared, then FIQs and IRQs may still be used,

but it is not possible to nest IRQs or FIQs. Neither is it possible

to set an interrupt source priority level. In this default state, an

FIQ does have a higher priority than an IRQ.

Name:

IRQCONN

Address:

0xFFFF0030

Default value:

0x00000000

Access:

Read and write

Table 95. IRQCONN MMR Bit Designations

Bit

Name

Description

31 to 2

Reserved

These bits are reserved and should not be

written to.

ENFIQN

This bit is set to 1 to enable nesting of FIQ

interrupts.

This bit is cleared to mean no nesting or

prioritization of FIQs is allowed.

ENIRQN

This bit is set to 1 to enable nesting of IRQ

interrupts.

When this bit is cleared, it means no

nesting or prioritization of IRQs is

allowed.

IRQSTAN Register

If IRQCONN Bit 0 is asserted and IRQVEC is read then one of

these bits is asserted. The bit that asserts depends on the priority of

the IRQ. If the IRQ is of Priority 0, then Bit 0 asserts. If the IRQ is

of Priority 1, then Bit 1 asserts, and so forth. When a bit is set in

this register, all interrupts of that priority and lower are

blocked.

To clear a bit in this register, all bits of a higher priority must be

cleared first. It is only possible to clear one bit at a time. For

example, if this register is set to 0x09, then writing 0xFF changes

the register to 0x08, and writing 0xFF a second time changes the

Name:

IRQSTAN

Address:

0xFFFF003C

Default value:

0x00000000

Access:

Read and write

Table 96. IRQSTAN MMR Bit Designations

Bit

Name

Description

31 to 8

Reserved

These bits are reserved and should not be

written to.

7 to 0

This bit is set to 1 to enable nesting of FIQ

interrupts.

When this bit is cleared, it means no

nesting or prioritization of FIQs is

allowed.

FIQVEC Register

The FIQ interrupt vector register, FIQVEC, points to a memory

address containing a pointer to the interrupt service routine of

the currently active FIQ. This register should only be read when

an FIQ occurs and FIQ interrupt nesting has been enabled by

setting Bit 1 of the IRQCONN register.

Name:

FIQVEC

Address:

0xFFFF011C

Default value:

0x00000000

Access:

Read only

Table 97. FIQVEC MMR Bit Designations

Bit

Type

Initial

Value

Description

31 to 23

Read only

Always read as 0.

22 to 7

R/W

IRQBASE register value.

6 to 2

Highest priority source. This

is a value between 0 and 27

that represents the possible

interrupt sources. For

example, if the highest

currently active FIQ is

Timer 2, then these bits are

[00100].

1 to 0

Reserved

Reserved bits.

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