SPC582BX datasheet(101/115 Pages) STMICROELECTRONICS

101 / 115 page

DS11597 Rev 4

101/115

SPC582Bx

Package information

103

5.5.3

QFN48

5.5.4

General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from the equation:

Equation 1

TJ = TA + (RθJA * PD)

where:

TA = ambient temperature for the package (°C)

RθJA = junction-to-ambient thermal resistance (°C/W)

PD = power dissipation in the package (W)

The thermal resistance values used are based on the JEDEC JESD51 series of standards

to provide consistent values for estimations and comparisons. The differences between the

values determined for the single-layer (1s) board compared to a four-layer board that has

two signal layers, a power and a ground plane (2s2p), demonstrate that the effective

thermal resistance is not a constant. The thermal resistance depends on the:

•

Construction of the application board (number of planes)

•

Effective size of the board which cools the component

•

Quality of the thermal and electrical connections to the planes

•

Power dissipated by adjacent components

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

Table 56. Thermal characteristics for QFN48 package

Symbol

Parameter(1)

Conditions

Value(2)

Unit

RθJA

D Junction-to-Ambient, Natural Convection(3) Four layer board (2s2p)

43.9

°C/W

RθJB

Junction-to-board(4)

—28.8

°C/W

RθJCtop

Junction-to-case top(5)

—28.9

°C/W

RθJCbottom CC D

Junction-to-case bottom(6)

—22.5

°C/W

ΨJT

Junction-to-package top(7)

Natural convection

11.5

°C/W

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. These values are preliminary, therefore they are subject to change.

3. Per JEDEC JESD51 with the board (JESD51-7) horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the top case surface in ideal contact and measured by cold plate as per JEDEC

best practice guidelines (JESD51-12).

6. Thermal resistance between the die and the bottom case surface in ideal contact and measured by cold plate as per

JEDEC best practice guidelines (JESD51-12).

7. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

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