SPC582BX datasheet(68/115 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC582Bx

68/115

DS11597 Rev 4

4.15.2.1

DSPI master mode full duplex timing with CMOS pads

4.15.2.1.1 DSPI CMOS master mode – classic timing

Note:

In the following table, all output timing is worst case and includes the mismatching of rise

and fall times of the output pads.

Table 37. DSPI channel frequency support

DSPI use mode(1)

Max usable

frequency

(MHz)(2),(3)

CMOS (Master

mode)

Full duplex – Classic timing (Table 38)

DSPI_0, DSPI_1,

DSPI_2, DSPI_3,

Full duplex – Modified timing (Table 39)

DSPI_0, DSPI_1,

DSPI_2, DSPI_3,

Output only mode (SCK/SOUT/PCS) (Table 38 and

Table 39)

DSPI_0, DSPI_1,

DSPI_2, DSPI_3,

Output only mode TSB mode (SCK/SOUT/PCS)

DSPI_0, DSPI_1,

DSPI_2, DSPI_3,

CMOS (Slave mode Full duplex) (Table 40)—

1. Each DSPI module can be configured to use different pins for the interface. Refer to the device pinout Microsoft Excel file

attached to the IO_Definition document for the available combinations. It is not possible to reach the maximum

performance with every possible combination of pins.

2. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.

3. Maximum usable frequency does not take into account external device propagation delay.

Table 38. DSPI CMOS master classic timing (full duplex and output only)

MTFE = 0, CPHA = 0 or 1

Symbol

C Characteristic

Condition

Value(1)

Unit

Pad drive(2)

Load (CL)Min

Max

1tSCK

CC D SCK cycle time

SCK drive strength

Very strong

25 pF

59.0

—

Strong

50 pF

80.0

—

Medium

50 pF

200.0

—

2tCSC

CC D

PCS to SCK

delay

SCK and PCS drive strength

Very strong

25 pF

(N(3) × tSYS(4))–

—

Strong

50 pF

(N(3) × tSYS(4))–

—

Medium

50 pF

(N(3) × tSYS(4))–

—

PCS medium

and SCK

strong

PCS = 50 pF

SCK = 50 pF

(N(3) × tSYS(4))–

—

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