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SPC582BX датащи(PDF) 70 Page - STMicroelectronics

номер детали SPC582BX
подробное описание детали  SPC58 2B Line - 32 bit Power Architecture automotive MCU Single core 80Mhz, 1MByte Flash, ASIL-B
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производитель  STMICROELECTRONICS [STMicroelectronics]
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SPC582BX датащи(HTML) 70 Page - STMicroelectronics

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Electrical characteristics
SPC582Bx
70/115
DS11597 Rev 4
SOUT data hold time (after SCK edge)
10
tHO
CC D
SOUT data hold
time after SCK(9)
SOUT and SCK drive strength
Very strong
25 pF
–7.7
ns
Strong
50 pF
–11.0
Medium
50 pF
–15.0
1. All timing values for output signals in this table are measured to 50% of the output voltage.
2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS =10ns).
5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).
6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
7. PCSx and PCSS using same pad configuration.
8. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL voltage thresholds.
9. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.
Table 38. DSPI CMOS master classic timing (full duplex and output only)
MTFE = 0, CPHA = 0 or 1 (continued)
#
Symbol
C Characteristic
Condition
Value(1)
Unit
Pad drive(2)
Load (CL)Min
Max



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