STM32G070CB datasheet(25/93 Pages) STMICROELECTRONICS

25 / 93 page

DS12766 Rev 2

25/93

STM32G070CB/KB/RB

Functional overview

3.16

Real-time clock (RTC), tamper (TAMP) and backup registers

The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of

the silicon die.

The ways of powering the RTC domain are described in Section 3.7.6.

The RTC is an independent BCD timer/counter.

Features of the RTC:



Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format



Automatic correction for 28, 29 (leap year), 30, and 31 days of the month



Programmable alarm



On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with

a master clock



Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be

used to improve the calendar precision



Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal

inaccuracy



Two anti-tamper detection pins with programmable filter



Timestamp feature to save a calendar snapshot, triggered by an event on the

timestamp pin or a tamper event, or by switching to VBAT mode



17-bit auto-reload wakeup timer (WUT) for periodic events, with programmable

resolution and period



Multiple clock sources and references:

–

A 32.768 kHz external crystal (LSE)

–

An external resonator or oscillator (LSE)

–

The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)

–

The high-speed external clock (HSE) divided by 32

When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When

clocked by LSI, the RTC does not operate in VBAT mode, but it does in low-power modes.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt

and wake the device up from the low-power modes.

The backup registers allow keeping 20 bytes of user application data in the event of VDD

failure, if a valid backup supply voltage is provided on VBAT pin. They are not affected by

the system reset, power reset, and upon the device’s wakeup from Standby mode.

3.17

Inter-integrated circuit interface (I2C)

The device embeds two I2C peripherals. Refer to Table 7 for the features.

The I2C-bus interface handles communication between the microcontroller and the serial

I2C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing.

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