STM32G070CB datasheet(71/93 Pages) STMICROELECTRONICS

71 / 93 page

DS12766 Rev 2

71/93

STM32G070CB/KB/RB

Electrical characteristics

Figure 18. ADC accuracy characteristics

Figure 19. Typical connection diagram using the ADC

1. Refer to Table 52: ADC characteristics for the values of RAIN and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (refer to Table 47: I/O static characteristics for the value of the pad capacitance). A high

Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

3. Refer to Table 47: I/O static characteristics for the values of Ilkg.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 8: Power supply scheme.

The 100 nF capacitor should be ceramic (good quality) and it should be placed as close as

possible to the chip.

1. Based on characterization results, not tested in production.

2. ADC DC accuracy values are measured after internal calibration.

3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion

of signal on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins

susceptible to receive negative current.

4. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V

and disabled when VDDA ≥ 2.4 V.

MSv19880V3

(1) Example of an actual transfer curve

(2) Ideal transfer curve

(3) End point correlation line

4095

4094

4093

345

4093 4094

4095

1 LSB ideal

(1)

(3)

(2)

Code

(VAIN / VREF+)*4095

ET total unadjusted error: maximum deviation

between the actual and ideal transfer curves.

EG gain error: deviation between the last ideal

transition and the last actual one.

ED differential linearity error: maximum deviation

between actual steps and the ideal ones.

EL integral linearity error: maximum deviation between

any actual transition and the end point correlation line.

EO offset error: maximum deviation between the

first actual transition and the first ideal one.

MS33900V5

Sample and hold ADC converter

12-bit

converter

Cparasitic

(2)

Ilkg

(3)

CADC

VDDA

RAIN

(1)

VAIN

AINx

RADC

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