AT25QL641 datasheet(31/77 Pages) DIALOG

номер детали	AT25QL641

подробное описание детали	64-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	77 Pages

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AT25QL641

DS-25QL641–130E–10/2018

Figure 7-20. Fast Read Quad I/O Instruction (Initial instruction or previous M7-0 ≠ Axh, QPI mode, 80 MHz)

Figure 7-21. Fast Read Quad I/O Instruction (Initial instruction or previous M7-0 ≠ Axh, QPI mode, 133 MHz)

7.15

Page Program (02h)

The Page Program instruction is for programming the memory to be “0”. A Write Enable instruction must be issued

before the device accept the Page Program Instruction (Status Register bit WEL= 1). After the Write Enable (WREN)

instruction has been decoded, the device sets the Write Enable Latch (WEL). The instruction is entered by driving the

CS pin low and then sending the instruction code “02h” with following a 24-bits address (A23-A0) and at least one data

byte, into the SI pin. The CS pin must be driven low for the entire time of the instruction while data is being sent to the

device. (Please refer to Figure 7-22 and Figure 7-23).

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set

to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing

wraps around to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed

without having any effect on other bytes within the same page. One condition to perform a partial page program is that

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