AT25QL641 datasheet(6/77 Pages) DIALOG

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AT25QL641

DS-25QL641–130E–10/2018

HOLD

(I/O

HOLD

The HOLD pin is used to temporarily pause serial communication without deselecting or

resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on

the SI pin are ignored and the SO pin is placed in a high-impedance state.

The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold

condition to start. A Hold condition pauses serial communication only and does not have an

effect on internally self-timed operations such as a program or erase cycle.

With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input pin (I/O

and with other pins, allows four bits (on I/O

3-0) of data to be clocked in on every rising edge of

SCK. With the Quad-Output Read commands, the HOLD Pin becomes an output pin (I/O3) in

conjunction with other pins to allow four bits of data on (I/O3

3-0) to be clocked in on every

falling edge of SCK.

To maintain consistency with SPI nomenclature, the HOLD (I/O3) pin is referenced as the

HOLD pin unless specifically addressing the Quad-I/O modes in which case it is referenced as

I/O

3. The HOLD pin is internally pulled-high and may be left floating if the Hold function is not

used. However, it is recommended that the HOLD pin also be externally connected to VCC

whenever possible.

Input/Output

DEVICE POWER SUPPLY: VCC is the supply voltage. It is the single voltage used for all

device functions including read, program, and erase. The V

CC pin is used to supply the

source voltage to the device. Operations at invalid V

CC voltages may produce spurious results

and should not be attempted.

Power

GND

GROUND:

SS is the reference for the VCC supply voltage. The ground reference for the

power supply. GND should be connected to the system ground.

Power

Table 1-1.

Pin Descriptions (Continued)

Symbol

Name and Function

Asserted

State

Type

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