AT25QL641 datasheet(27/77 Pages) DIALOG

номер детали	AT25QL641

подробное описание детали	64-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	77 Pages

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производитель	DIALOG [Dialog Semiconductor]

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AT25QL641

DS-25QL641–130E–10/2018

Figure 7-15. Fast Read Quad Output Instruction (SPI Mode)

7.13

Fast Read Dual I/O (BBh)

The Fast Read Dual I/O instruction reduces cycle overhead through double access using two I/O pins: I/O0 and I/O1.

Continuous read mode

The Fast Read Dual I/O instruction can further reduce cycle overhead through setting the Mode bits (M7-0) after the

input Address bits (A23-0). The upper nibble of the Mode (M7-4) controls the length of the next Fast Read Dual I/O

instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode (M3-0)

are don’t care (“X”), However, the I/O pins should be high-impedance prior to the falling edge of the first data out clock.

If the Mode bits (M7-0) equal “Ax” hex, then the next Fast Dual I/O instruction (after CS is raised and then lowered) does

not require the instruction (BBh) code, as shown in Figure 7-16 and Figure 7-17. This reduces the instruction sequence

by eight clocks and allows the address to be immediately entered after CS is asserted low. If Mode bits (M7-0) are any

value other “Ax” hex, the next instruction (after CS is raised and then lowered) requires the first byte instruction code,

thus returning to normal operation. A mode bit reset can be used to reset t h e mode bits (M7-0) before issuing

normal instructions.

AT25QL641 датащи(PDF) 27 Page - Dialog Semiconductor