AT25QL641 datasheet(29/77 Pages) DIALOG

номер детали	AT25QL641

подробное описание детали	64-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	77 Pages

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AT25QL641

DS-25QL641–130E–10/2018

7.14

Fast Read Quad I/O (EBh)

The Fast Read Quad I/O instruction reduces cycle overhead through quad access using four I/O pins: I/O0, I/O1, I/O2, and

I/O3. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast read Quad I/O Instruction.

Continuous read mode

The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the Mode bits (M7-0) with

following the input address bits (A23-0), as shown in Figure 7-18. The upper nibble of the mode (M7-4) controls the

length of the next ‘Fast Read Quad I/O’ instruction through the inclusion or exclusion of the first byte instruction code.

The lower nibble bits of the Mode (M3-0) are don’t care (“X”). However, the I/O pins should be high-impedance prior to

the falling edge of the first data out clock.

If the Mode bits (M7-0) equal “Ax” hex, then the next Fast Read Quad I/O instruction (after CS is raised and then

lowered) does not require the EBh instruction code, as shown in Figure 7-19. This reduces the instruction sequence by

eight clocks and allows the address to be immediately entered after CS is asserted low. If the Mode bits (M7-0) are any

value other than “Ax” hex, the next instruction (after CS is raised and then lowered) requires the first byte instruction

code, thus retuning normal operation. A Mode Bit Reset can be used to reset Mode Bits (M7-0) before issuing normal

instructions.

Figure 7-18. Fast Read Quad I/O Instruction (Initial instruction or previous M7-0 ≠ Axh, SPI mode)

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