VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-88
VGA Extended Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
GR26 – DPMS Control .....................................................RW
7-6
RAMDAC Internal Power Control
00 Normal ...................................................default
01 DAC off (used in LCD only mode)
10 Standby (DAC off, LUT in low power mode,
I/O allowed to LUT). May be used in LUT
bypass mode.
11 Suspend (DAC off, LUT access disallowed
but LUT contents are preserved)
5-4
Reserved
........................................ always reads 0
3
DPMS Control
0
Software Control Mode: DPMS controlled by
GR23[1-0] in simultaneous display and CRT-
only modes (may be used to decouple the
power modes of the CRT and LCD during
simultaneous display) ..........................default
1
Hardware Control Mode:
DPMS controlled
by internal power states.
2-0
Reserved
........................................ always reads 0
DPMS Control Modes
DPMS Software Control Mode
In simultaneous display mode, the software control mode can
be used to control DPMS low power states independent of the
chip power states.
In CRT display mode, software mode
gives total DPMS control to software. Pseudo-standby may
be controlled by bits 7 and 6, as well as BLANK# timing.
DPMS Hardware Control Mode
Table 9. DPMS Sequence - Hardware Timer Mode
Power Level
DPMS Mode
High - Activity detected
On
Moderate - 16 min inactivity
Standby
Low - 32 min inactivity
Suspend
Lowest - 64 min inactivity
Off
DPMS hardware timer mode is defined as CRT only mode
with the DPMS control mode bit set to hardware (bit 3 =1).
Activity detection is set by register GR21[2:0]. Status is
indicated in bits 1 and 0. The timer may be controlled by
software from GR20[7].
Table 10. DPMS Sequence - Hardware Mode in
Simultaneous Display Mode
Power Level
DPMS Mode
High - Chip on state
On
Moderate - Chip standby
Off
Low - Chip suspend
Off
Lowest - Chip off state
Off
In simultaneous display mode with hardware DPMS
set, DPMS states are sequenced by the timer, pin, and
register bits that control the chip power states.
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