VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-39-
Device 0 Bus 0 Host Bridge Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
Device 0 Offset 59-58 - DRAM MA Map Type...............RW
15-13 Bank 5/4 MA Map Type (EDO/FPG)
000 8-bit Column Address
001 9-bit Column Address
010 10-bit Column Address ..........................default
011 11-bit Column Address
100 12-bit Column Address (64Mb)
101 Reserved
11x Reserved
Bank 5/4 MA Map Type (SDRAM)
0xx 16Mb SDRAM .......................................default
100 64/128Mb SDRAM (x4, x8, x16, 4-bank x32)
101 64Mb VC SDRAM(x4)
110 64/128Mb VC SDRAM (8Mx8 or 8Mx16)
111 128Mb VC SDRAM (16Mx8)
12
Bank 5/4 Virtual Channel Enable............. default=0
11-8 Reserved
........................................ always reads 0
7-5
Bank 1/0 MA Map Type (see above)
4
Bank 1/0 Virtual Channel Enable............. default=0
3-1
Bank 3/2 MA Map Type (see above)
0
Bank 3/2 Virtual Channel Enable............. default=0
Device 0 Offset 5A-5F – DRAM Row Ending Address:
All of the registers in this group default to 01h:
Offset 5A – Bank 0 Ending (HA[30:23]) ....................RW
Offset 5B – Bank 1 Ending (HA[30:23]).....................RW
Offset 5C – Bank 2 Ending (HA[30:23]) ....................RW
Offset 5D – Bank 3 Ending (HA[30:23]) ....................RW
Offset 5E – Bank 4 Ending (HA[30:23]).....................RW
Offset 5F – Bank 5 Ending (HA[30:23]).....................RW
Note :BIOS is required to fill the ending address registers
for all banks even if no memory is populated. The
endings have to be in incremental order.
Device 0 Offset 60 – DRAM Type ................................... RW
7-6
Reserved
........................................ always reads 0
5-4
DRAM Type for Bank 5/4
00 Fast Page Mode DRAM (FPG).............. default
01 EDO DRAM (EDO)
10 Reserved
11 SDRAM
3-2
DRAM Type for Bank 3/2.....................default=FPG
1-0
DRAM Type for Bank 1/0.....................default=FPG
Table 4. Memory Address Mapping Table
EDO/FP DRAM
MA: 13 12 11 10 9
8
7
6
5
4
3
2
1
0
8-bit Col
(000)
23 22 21 11 20 19
10
18
9
17
8
16
7
15
6
14
5
13
4
12
3
Row Bits
Col Bits
9-bit Col
(001)
24 23 22 21 20
11
19
10
18
9
17
8
16
7
15
6
14
5
13
4
12
3
Row Bits
Col Bits
10-bit Col
(010)
25 24 23 21
22
20
11
19
10
18
9
17
8
16
7
15
6
14
5
13
4
12
3
Row Bits
Col Bits
11-bit Col
(011)
26 25 23
24
21
22
20
11
19
10
18
9
17
8
16
7
15
6
14
5
13
4
12
3
Row Bits
Col Bits
12-bit Col
(100)
27 25
26
23
24
21
22
20
11
19
10
18
9
17
8
16
7
15
6
14
5
13
4
12
3
Row Bits
Col Bits
SDRAM
MA: 13 12 11 10 9
8
7
6
5
4
3
2
1
0
16Mb (0xx)
11
11
22
PC
21
24
20
23
19
10
18
9
17
8
16
7
15
6
14
5
13
4
12
3
Row Bits
Col Bits
64Mb (100)
2/4 bank
x4, x8, x16;
4-bank x32
24
24
13
13
12
12
22
PC
21
26
20
25
19
10
18
9
17
8
16
7
15
6
14
5
11
4
23
3
x4: 10 col
x8: 9 col
x16: 8 col
x32: 8 col
VC SDRAM
Segment address {HA9,HA10,HA25,HA26} depends on VC
SDRAM configurations.
MA: 13 12 11 10 9
8
7
6
5
4
3
2
1
0
64M
VC SDRAM
24 13 12 22 21 20 19 18 17 16 15 14 11 23
64M: 4Mx16
(13x6)
(101) 6-bit Cola
2-bank
24 13 12 PC 26 25 10 9
87
6543
64M/128M
VC SDRAM
24 13 12 22 21 20 19 18 17 16 15 14 11 23
64M: 8Mx8
(13x7)
(110) 7-bit Cola
2-bank
24 13 12 PC 26 25 10 987
6543
128M: 8Mx16
(13x7)
128M
VC SDRAM
24 13 12 22 21 20 19 18 17 16 15 14 11 23 128M: 16Mx8
(13x8)
(111) 8-bit Cola
2-bank
24 13 12 PC 26 25 10 987
6543
"PC" = "Precharge Control" (refer to SDRAM specifications)
16Mb 11x10, 11x9, and 11x8 configurations supported
64Mb x4:
12x10 4bank, 13x10 2bank
x8:
12x9 4bank,
13x9 2bank
x16: 12x8 4bank,
13x8 2bank
x32: 11x8 4bank
128Mb same as 64Mb
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
