VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-16-
Pinouts
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DRAM Interface
Signal Name
Pin #
I/O
Signal Description
MD[63:0]
see pin list
IO
Memory Data. These signals are connected to the DRAM data bus.
Note:
MD0 is internally pulled up for use in EDO memory type
detection.
MA[14:0]
/ Strap Options
AF25, AE25,
AE24, AD24,
AE26, AD25,
AD26, AC24,
AC25, AC26,
AB24, AB25,
AB26, AB23,
AA23
O / I
Memory Address. DRAM address lines. These pins are also used for
power-up strapping options (sampled on the rising edge of RESET#):
MA14,12 Rx68[1-0] CPU FSB Freq (0=66, 1=100, 2=auto, 3=133)
MA13
Rx52[7]
GTL I/O Buffer Pullup (0=Disable, 1=Enable)
MA11
In-order Queue Depth (0=1-level, 1=4-level)
MA10-9
North Bridge Clock Delay (0-3 Clocks)
MA8, 6
Graphics Clock Select (0=Normal, 1-3=Test)
MA7
Graphics Test Mode (0=Normal, 1=Test)
MA5
LCD Output (0=Off, 1=On)
MA4-2
Panel Type (0-3=TFT, 4-7=DSTN)
MA1-0
Graphics Clock Delay (0-3 Clocks)
All pins have internal pull-downs for default low (0).
Strap 1 using 4.7K
Ω TO VCC3.
CKE5# / SRASB#,
CKE4# / SRASC#,
CKE3# / SCASB#,
CKE2# / SWEB#,
CKE1# / SCASC#,
CKE0# / SWEC#
AA25,
AA26,
V25,
U25,
V24,
U26
IO
SDRAM Clock Enable. Clock enables 5-0 may be connected to the
DRAM modules in any order. Each DRAM module requires 2 clock
enables.
Note: These pins are powered by VSUS
RAS[5-0]# / CS[5-0]#
W21, Y22,
Y23, Y24,
Y25, Y26
O
Multifunction Pins
1. FPG/EDO DRAM: Row Address Strobe of each bank.
2. Synchronous DRAM: Chip select of each bank.
Note: These pins are powered by VSUS.
CAS#[7:0] / DQM[7:0]
AF23, AD23,
W25, W26,
AE23, AF24,
W23, V23
O
Multifunction Pins
1. FPG/EDO DRAM: Column Address Strobe of each byte lane.
2. Synchronous DRAM: Data mask of each byte lane.
Note: These pins are powered by VSUS.
SRASA#,
SRASB# / CKE5,
SRASC# / CKE4
AA24,
AA25,
AA26
O
Row Address Command Indicator.
For support of up to three
Synchronous DRAM DIMM slots (these are copies of the same logical
signal). “A” controls banks 0-1 (module 0), “B” controls banks 2-3
(module 1), and “C” controls banks 4-5 (module 2).
SCASA#,
SCASB# / CKE3
SCASC# / CKE1
U22,
V25,
V24
O
Column Address Command Indicator. For support of up to three
Synchronous DRAM DIMM slots (these are copies of the same logical
signal). “A” controls banks 0-1 (module 0), “B” controls banks 2-3
(module 1), and “C” controls banks 4-5 (module 2).
SWEA# / MWEA#,
SWEB# / MWEB# / CKE2,
SWEC# / MWEC# / CKE0
U24,
U25,
U26
O
Write Enable Command Indicator.
For support of up to three
Synchronous DRAM DIMM slots (these are copies of the same logical
signal).
Multifunction pins, used as MWE# pins for FPG/EDO
memory. “A” controls banks 0-1 (module 0), “B” controls banks 2-3
(module 1), and “C” controls banks 4-5 (module 2). Note: These pins
are powered by VSUS.
Note: Clocking of the memory subsystem uses memory clock (MCLK); see the clock pin group at the end of the pin descriptions
section for descriptions of the clock pins.
Note: Connect all memory interface pins except MD to the DRAM modules through 22
Ω series resistors (see the Apollo ProMedia
Design Guide” for more specific connection details and PCB layout recommendations).
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