VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-76
VGA Extended Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
SRE – Mode Control 1 (Old)............................................RW
7
Reserved
.......................................always reads 1
6
IRQ Polarity Select
0
Active High ............................................default
1
Active Low
5
Configuration Port (SR0C) Select
0
Select Port 2
1
Select Port 1 ..........................................default
4
Reserved
........................................ always reads 0
3
Memory Bus .........................................................RO
08-bit
1
16-bit .......................................always reads 1
2-1
256K Bank Select
00 Bank 0 ....................................................default
01 Bank 1
10 Bank 2
11 Bank 3
Note: an inverted value will be written to bit-1
These bits (and 3C2[5]) are write enabled when
GR06[3-2] = 00. 3C2[5] is used as a page select to
select one of the two 64KB pages.
0
RAMDAC Pixel Clock Invert
0
Normal ...................................................default
1
Invert pixel clock to RAMDAC
SRE – Mode Control 1 (New)...........................................RW
7
Configuration Port Write Enable ........... default = 0
0
Write Protect
1
Write Enable
Ports effected: SRC, SRF, CR28-2A, SRE_New[6-4]
(this register), and SR10[0]
6
CPU Bandwidth Select for Text Mode
0
132-Column Text
1Other Text .............................................default
5-0
64K Bank Select ....................................... default = 0
Bit-1 should be inverted when performing writes
These bits are enabled when GR06[3-2] are written
with any value other than 00.
SRF – Power-up Mode 2 .................................................. RW
This register is write protected by SRE_New[7].
7
Reserved
...................................... always reads 1
6
BIOS Control
0
Disabled ................................................. default
1Enabled
5
Palette Mode
0
Master Abort Mode
1
Intel Retry Mode................................... default
4
Linear / Bank Addressing Control
0
Linear Only
1
Linear / Bank ........................................ default
3-0
Reserved for BIOS ............................ default = 1111
SR10 – VESA™ Big BIOS Control ................................. RW
7
Extended VESA™ Big BIOS Enable
0
Disabled ................................................ default
1Enabled
6-5
Video Address Select ........................................... RO
00 A0000-A7FFF ....................................... default
01 -reserved-
10 B0000-B7FFF
11 B8000-BFFFF
These bits are decoded from GR6[3-2]
4-1
Reserved
........................................ always reads 0
0
Page Select
0
Select the original C0000-C7FFF access ..... def
1
Select extended access defined by bits 6-5
Bit-0 of this register is write protected by SRE_New[7].
SR11 – Protection
........................................................ RW
7-0
Register Protection Enable .................... default = 00
87 Unprotect all extended registers except those
which may still be protected by SRE_New[7]
92 Unprotect all extended registers independent
of SRE_New[7]
If any value other than the ones listed above is
programmed into this register, all extended registers
will be write protected.
SR12 – Threshold
........................................................ RW
7-4
Queue Threshold Playback and Capture .....def = 2
Threshold of the display queue when both playback
and capture are enabled (for definition see SRD.new).
3-0
Queue Threshold Playback or Capture........def = 1
Threshold of the display queue when either playback
or capture are enabled (for definition see SRD.new)
The old threshold is used when neither playback nor capture is
enabled.
All three thresholds cannot be set to 0.
Other
definitions are the same as the original.
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