VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-41-
Device 0 Bus 0 Host Bridge Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
Device 0 Offset 64 - DRAM Timing for Banks 0,1 .........RW
Device 0 Offset 65 - DRAM Timing for Banks 2,3 .........RW
Device 0 Offset 66 - DRAM Timing for Banks 4,5 .........RW
FPG / EDO Settings for Registers 64-66
7
RAS Precharge Time
03T
1
4T
.....................................................default
6
RAS Pulse Width
04T
1
5T
.....................................................default
5-4
CAS Read Pulse Width
00 1T
01 2T
10 3T
.....................................................default
11 4T
Note: EDO will not automatically reduce the CAS
pulse width. For EDO type DRAMs, use 00 if CAS
width = 1 is to be used.
3
CAS Write Pulse Width
01T
1
2T
.....................................................default
2
MA-to-CAS Delay
01T
1
2T
.....................................................default
1
RAS to MA Delay
0
1T
.....................................................default
12T
0
Reserved
........................................ always reads 0
SDRAM Settings for Registers 64-66
7
Precharge Command to Active Command Period
0TRP = 2T
1TRP = 3T ................................................default
6
Active Command to Precharge Command Period
0TRAS = 5T
1TRAS = 6T ..............................................default
5-4
CAS Latency
00 1T
01 2T
10 3T
.....................................................default
11 Reserved
3
Reserved (Do Not Program).................... default = 0
2
ACTIVE Command to CMD Command Period
02T
1
3T
.....................................................default
1-0
Bank Interleave
00 No Interleave..........................................default
01 2-way
10 4-way
11 Reserved
Device 0 Offset 68 - DRAM Control ............................... RW
7
SDRAM Open Page Control
0
Always
precharge
SDRAM
banks
when
accessing EDO/FPG DRAMs ................ default
1
SDRAM banks remain active when accessing
EDO/FPG banks
6
Bank Page Control
0
Allow only pages of the same bank active ... def
1
Allow pages of different banks to be active
5
EDO Pipeline Burst Rate
0
X-2-2-2-2-2-2-2 ..................................... default
1
X-2-2-2-3-2-2-2
4
DRAM Data Latch Delay for EDO/FPG DRAM
0
Latch DRAM data at CCLK rising edge..... def.
1
Delay latch of DRAM data by ½ CCLK
3EDO Test Mode
0
Disable................................................... default
1Enable
Note: MD0 is internally pulled up for EDO detection.
2
Burst Refresh
0
Disable................................................... default
1
Enable (burst 4 times)
1-0
System Frequency Divider...................................RO
00 CPU/PCI Frequency Ratio = 2x
(66 MHz)
01 CPU/PCI Frequency Ratio = 3x
(100 MHz)
10 CPU/PCI Frequency Ratio Auto Detect
11 CPU/PCI Frequency Ratio = 4x
(133 MHz)
These bits are latched from MA[14, 12] at the rising
edge of RESET#.
Without external strapping
resistors, the default setting of these bits is 00 (66
MHz).
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