VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-96
VGA Extended Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
Additional CRTC Extended Registers
CR51 – Bus Grant Termination Control.........................RW
7-0
Bus Grant Termination Position
This regiester is active if CR52[6] = 1
CR52 – Shared Frame Buffer Control ............................RW
7, 5
Shared Frame Buffer (SFB)
00 Disable ...................................................default
01 Enable SFB slave mode 1 (8ma I/O buffer)
10 Enable SFB master mode
11 Enable SFB slave mode 2 (16ma I/O buffer)
6
Bus Grant Termination Position Control
0
Disable ...................................................default
1Enable
4
Reserved
........................................ always reads 0
3-0
Bus Grant Low Pulse (MCLKs) ...........def = 0010b
CR55 – PCI Retry Control ...............................................RW
7
PCI Retry in Memory Write Command
0
Disable ...................................................default
1Enable
6
PCI Retry in Memory Read Command
0
Disable ...................................................default
1Enable
5-0
Number of PCICLKs * 2 for STOP#....... def = 0Fh
Number of PCICLKs, multiplied by 2, for generating
STOP# during the first data phase
CR56 – Display Pre-end Fetch Control ...........................RW
7-2
Reserved
........................................ always reads 0
1
Display Queue Pre-end Fetch
0
Disable ...................................................default
1Enable
0
Display Queue Pre-end Fetch Parameter Bit-8
Used with CR57 ......................................... default = 0
CR57 – Display Pre-end Fetch Parameter ......................RW
7-0
Display Queue Pre-end Fetch Parameter Bit-8
Used with CR56[0] .....................................default n/a
CR5E – Capture / ZV Port Control ................................ RW
7
Capture Idle ......................................................... RO
6
Capture Command Port
0
Disable................................................... default
1
Enable new command port (2203-2200h)
5-3
Reserved
........................................ always reads 0
2
PCI I/O Write Retry
0
Disable................................................... default
1Enable
1
PCI I/O Read Retry
0
Disable................................................... default
1Enable
0
Capture Interface
0
Disable................................................... default
1Enable
This bit is protected by SRE_New[7]
CR5F – Test Control ........................................................ RW
7
Internal Control Test Output
0
Normal................................................... default
1
Internal control signals are output to P15-0
P15
GEREQ
P14
GEBUSY
P13
CMDIN
P12
GEWAIT
P11
CMATCH
P10
KGECYC
P9
WBMT
P8
GERTRY
P7
BLANKTV
P6
WRSTY
P5
WRSTU
P4
WRSTV
P3
WRST1
P2
Y0EN
P1
UEN
P0
YUVEN
6
Capture Input Interrupt Polarity Select
0
Normal................................................... default
1
Test data is output to pixel bus P15-0
5-1
Reserved
........................................ always reads 0
0
Stop DISPQ REQ Test
0
Normal................................................... default
1
Stop DISPQ REQ
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