ATMEGA640 datasheet(112/436 Pages) MICROCHIP

112 / 436 page

112

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

15.2.4

EIFR – External Interrupt Flag Register

• Bits 7:0 – INTF7:0: External Interrupt Flags 7 - 0

When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set (one). If the I-

bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are set (one), the MCU will jump to the

interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by

writing a logical one to it. These flags are always cleared when INT7:0 are configured as level interrupt. Note that

when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This

may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep

Modes” on page 71 for more information.

15.2.5

PCICR – Pin Change Interrupt Control Register

• Bit 2 – PCIE2: Pin Change Interrupt Enable 1

When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is

enabled. Any change on any enabled PCINT23:16 pin will cause an interrupt. The corresponding interrupt of Pin

Change Interrupt Request is executed from the PCI2 Interrupt Vector. PCINT23:16 pins are enabled individually by

the PCMSK2 Register.

• Bit 1 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is

enabled. Any change on any enabled PCINT15:8 pin will cause an interrupt. The corresponding interrupt of Pin

Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15:8 pins are enabled individually by

the PCMSK1 Register.

• Bit 0 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is

enabled. Any change on any enabled PCINT7:0 pin will cause an interrupt. The corresponding interrupt of Pin

Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7:0 pins are enabled individually by

the PCMSK0 Register.

Bit

0x1C (0x3C)

INTF7

INTF6

INTF5

INTF4

INTF3

INTF2

INTF1

IINTF0

EIFR

Read/Write

R/W

Initial Value

Bit

7654321

(0x68)

–

PCIE2

PCIE1

PCIE0

PCICR

Read/Write

RRRRR

R/W

Initial Value

0000000

ATMEGA640 датащи(PDF) 112 Page - Microchip Technology

ATMEGA640 датащи(HTML) 112 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL