AM29N323D datasheet(17/48 Pages) AMD

17 / 48 page

Am29N323D

August 8, 2002

the system was writing to the read mode. Once erasure

begins, however, the device ignores reset commands

until the operation is complete.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the bank to

which the system was writing to the read mode. If the

program command sequence is written to a bank that

is in the Erase Suspend mode, writing the reset

command returns that bank to the erase-suspend-read

mode. Once programming begins, however, the device

ignores reset commands until the operation is com-

plete.

The reset command may be written between the

sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to the read mode. If a bank entered

the autoselect mode while in the Erase Suspend mode,

writing the reset command returns that bank to the

erase-suspend-read mode.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to read several identifier codes at specific

addresses:

Table 4 shows the address and data requirements. The

autoselect command sequence may be written to an

address within a bank that is either in the read or

erase-suspend-read mode. The autoselect command

may not be written while the device is actively program-

ming or erasing in the other bank.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the

autoselect command. The bank then enters the

autoselect mode. The system may read at any address

within the same bank any number of times without ini-

tiating another autoselect command sequence.

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

Program Command Sequence

Programming is a four-bus-cycle operation. The

program command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program

algorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 4 shows the address

and data requirements for the program command

sequence.

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and addresses

are no longer latched. The system can determine the

status of the program operation by monitoring DQ7 or

DQ6/DQ2. Refer to the Write Operation Status section

for information on these status bits.

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should be

reinitiated once that bank has returned to the read

mode, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bit to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to

program to a bank faster than using the standard

program command sequence. The unlock bypass

command sequence is initiated by first writing two

unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. That

bank then enters the unlock bypass mode. A two-cycle

unlock bypass program command sequence is all that

is required to program in this mode. The first cycle in

this sequence contains the unlock bypass program

command, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. The host system may also initiate the chip

erase and sector erase sequences in the unlock

bypass mode. The erase command sequences are

four cycles in length instead of six cycles. Table 4

shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issu e the two-cycle unlock bypass reset

command sequence. The first cycle must contain the

Identifier Code

Address

Manufacturer ID

(BA)00h

Device ID

(BA)01h

Sector Protect Verify

(SA)02h

Revision ID

(BA)03h

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