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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC5410X датащи(PDF) 64 Page - NXP Semiconductors |
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LPC5410X датащи(HTML) 64 Page - NXP Semiconductors |
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64 / 95 page  LPC5410x All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 2.11 — 19 September 2019 64 of 95 NXP Semiconductors LPC5410x 32-bit ARM Cortex-M4/M0+ microcontroller 11.10 SPI interfaces The actual SPI bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for SPI master mode is 48 Mbit/s, and the maximum supported bit rate for SPI slave mode is 21 Mbit/s. Table 27. SPI dynamic characteristics[1] Tamb = 40 C to 105 C; CL = 30 pF balanced loading on all pins; SLEW = standard mode. Parameters sampled at the 50 % level of the rising or falling edge. Symbol Parameter Conditions Min Max Unit SPI master 1.62V VDD 2.0 V tDS data set-up time CCLK = 1 MHz to 12 MHz 0 - ns CCLK = 48 MHz to 60 MHz 0 - ns CCLK = 96 MHz 0 - ns tDH data hold time CCLK = 1 MHz to 12 MHz 14 - ns CCLK = 48 MHz to 60 MHz 12 - ns CCLK = 96 MHz 9 - ns tv(Q) data output valid time CCLK = 1 MHz to 12 MHz 0 7 ns CCLK = 48 MHz to 60 MHz 0 2 ns CCLK = 96 MHz 0 2 ns SPI slave 1.62V VDD 2.0 V tDS data set-up time CCLK = 1 MHz to 12 MHz 22 - ns CCLK = 48 MHz to 60 MHz 4 - ns CCLK = 96 MHz 4 - ns tDH data hold time CCLK = 1 MHz to 12 MHz 0 - ns CCLK = 48 MHz to 60 MHz 0 - ns CCLK = 96 MHz 0 - ns tv(Q) data output valid time CCLK = 1 MHz to 12 MHz 46 70 ns CCLK = 48 MHz to 60 MHz 30 37 ns CCLK = 96 MHz 30 36 ns SPI master 2.7 V VDD 3.6 V tDS data set-up time CCLK = 1 MHz to 12 MHz 0 - ns CCLK = 48 MHz to 60 MHz 0 - ns CCLK = 96 MHz 0 - ns tDH data hold time CCLK = 1 MHz to 12 MHz 10 - ns CCLK = 48 MHz to 60 MHz 8 - ns CCLK = 96 MHz 7 - ns tv(Q) data output valid time CCLK = 1 MHz to 12 MHz 0 6 ns CCLK = 48 MHz to 60 MHz 0 1 ns CCLK = 96 MHz 0 1 ns SPI slave 2.7V VDD 3.6 V tDS data set-up time CCLK = 1 MHz to 12 MHz 21 - ns CCLK = 48 MHz to 60 MHz 4 - ns CCLK = 96 MHz 3 - ns |
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