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LPC5410X датащи(PDF) 49 Page - NXP Semiconductors |
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LPC5410X датащи(HTML) 49 Page - NXP Semiconductors |
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49 / 95 page ![]() LPC5410x All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 2.11 — 19 September 2019 49 of 95 NXP Semiconductors LPC5410x 32-bit ARM Cortex-M4/M0+ microcontroller [1] The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled using PDRUNCFG register. All other blocks are disabled and no code accessing the peripheral is executed. [2] The supply currents are shown for system clock frequencies of 12 MHz. [3] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples. RTC disabled (RTC oscillator input grounded) Fig 12. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD Table 14. Typical peripheral power consumption[1][2][3] VDD = 3.3 V; Tamb = 25 °C Peripheral IDD in uA IRC 262 WDT OSC 2.0 Flash 200.0 BOD 2.0 CLKOUT 37 Table 15. Typical AHB/APB peripheral power consumption[3][4][5] VDD = 3.3 V; T = 25 °C Peripheral IDD in A IDD in A/MHz IDD in A/MHz AHB peripheral CPU: 12 MHz, sync APB bus: 12 MHz CPU: 96MHz, sync APB bus: 96 MHz GPIO0 [1] - 0.50 0.7 GPIO1 [1] - 0.42 0.52 DMA - 5.0 6.86 CRC - 0.42 0.50 MAILBOX - 0.17 0.20 ADC0 - 2.25 2.92 SCTimer/PWM - 5.08 7.07 |
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