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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC5410X датащи(PDF) 43 Page - NXP Semiconductors |
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LPC5410X датащи(HTML) 43 Page - NXP Semiconductors |
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43 / 95 page  LPC5410x All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 2.11 — 19 September 2019 43 of 95 NXP Semiconductors LPC5410x 32-bit ARM Cortex-M4/M0+ microcontroller 10.3 Power consumption Power measurements in Active, sleep, deep sleep, and power down modes were performed under the following conditions: • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIO DIR register. • Write 1 to the GPIO CLR register to drive the outputs LOW. • All peripherals disabled. Table 11. Static characteristics: Power consumption in active and sleep modes Tamb = 40 C to +105 C, unless otherwise specified.1.62 V VDD 3.6 V. Symbol Parameter Conditions Min Typ[1] Max Unit ARM Cortex-M0+ in active mode; ARM Cortex-M4 in sleep mode IDD supply current CoreMark code executed from SRAM; flash powered down CCLK = 12 MHz [2][4][6] - 1.2 - mA CCLK = 48 MHz [3][4][6] - 3.0 - mA CCLK = 84 MHz [3][4][6] - 4.5 - mA CCLK = 100 MHz [3][4][6] - 5.5 - mA CCLK = 150 MHz [3][4][6] -11.0 -mA IDD supply current CoreMark code executed from flash; CCLK = 12 MHz; 1 system clock flash access time. [2][4][6] - 1.5 - mA CCLK = 48 MHz; 3 system clock flash access time. [3][4][6] - 3.6 - mA CCLK = 84 MHz; 6 system clock flash access time. [3][4][6] - 5.4 - mA CCLK = 100 MHz; 7 system clock flash access time. [3][4][6] - 6.6 - mA CCLK = 150 MHz; 7 system clock flash access time. [3][4][6] - 14.0 - mA IDD supply current Calculating Fibonacci numbers executed from flash; CCLK = 12 MHz [2][4][5] - 1.5 - mA CCLK = 84 MHz [3][4][5] - 6.2 - mA CCLK = 96 MHz [3][4][5] - 7.2 - mA |
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