LPC5410X datasheet(21/95 Pages) NXP

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LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

21 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

7. Functional description

7.1 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and

D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is

dedicated for data access (D-code). The use of two core buses allows for simultaneous

operations if concurrent operations target different devices.

A multi-layer AHB matrix connects the CPU buses and other bus masters to peripherals in

a flexible manner that optimizes performance by allowing peripherals on different slaves

ports of the matrix to be accessed simultaneously by different bus masters. Connections

in the multilayer matrix are shown in Figure 3.

APB peripherals are connected to the AHB matrix via two APB buses using separate

slave ports from the multilayer AHB matrix. This allows for better performance by reducing

collisions between the CPU and the DMA controller, and also for peripherals on the

asynchronous bridge to have a fixed clock that does not track the system clock.

7.2 ARM Cortex-M4 processor

The ARM Cortex-M4 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M4 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and

divide, interruptable/continuable multiple load and store instructions, automatic state save

and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt

controller, and multiple core buses capable of simultaneous accesses.

A 3-stage pipeline is employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

7.3 ARM Cortex-M4 integrated Floating Point Unit (FPU)

The FPU fully supports single-precision add, subtract, multiply, divide, multiply and

accumulate, and square root operations. It also provides conversions between fixed-point

and floating-point data formats, and floating-point constant instructions.

The FPU provides floating-point computation functionality that is compliant with the

ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to

as the IEEE 754 standard.

7.4 Memory Protection Unit (MPU)

The Cortex-M4 includes a Memory Protection Unit (MPU) which can be used to improve

the reliability of an embedded system by protecting critical data within the user

application.

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory regions, allowing memory regions to be defined as read-only

and detecting unexpected memory accesses that could potentially break the system.

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