LPC5410X datasheet(2/95 Pages) NXP

2 / 95 page

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

2 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

2. Features and benefits



Dual processor cores: ARM Cortex-M4 and ARM Cortex-M0+. The M0+ core runs at

the same frequency as the M4 core. Both cores operate up to a maximum frequency of

150 MHz.



ARM Cortex-M4 core (version r0p1):



ARM Cortex-M4 processor, running at a frequency of up to 150 MHz, using the

same clock as the Cortex-M4.



Floating Point Unit (FPU) and Memory Protection Unit (MPU).



ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).



Non-maskable Interrupt (NMI) input with a selection of sources.



Serial Wire Debug with eight breakpoints and four watch points.

Includes Serial Wire Output for enhanced debug capabilities.



System tick timer.



ARM Cortex-M0+ core (version r0p1):



ARM Cortex-M0+ processor, running at a frequency of up to 100 MHz.



ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).



Non-maskable Interrupt (NMI) input with a selection of sources.



Serial Wire Debug with four breakpoints and two watch points.



System tick timer.



On-chip memory:



Up to 512 kB on-chip flash program memory with flash accelerator and 256 byte

page erase and write.



104 kB total SRAM composed of:



Up to 96 kB contiguous main SRAM.



An additional 8 kB SRAM.



ROM API support:



Flash In-Application Programming (IAP) and In-System Programming (ISP).



Power control API.



Serial interfaces:



Four USART interfaces with synchronous mode and 32 kHz mode for wake-up

from deep sleep and power down modes. The USARTs have FIFO support from

the System FIFO and share a fractional baud-rate generator.



Two SPI interfaces, each with four slave selects and flexible data configuration.

The SPIs have FIFO support from the System FIFO. The slave function is able to

wake up the device from deep sleep and power down modes.



Three I2C-bus interfaces supporting fast mode and Fast-mode Plus with data rates

of up to 1Mbit/s and with multiple address recognition and monitor mode. Each

I2C-bus interface also supports High Speed Mode (3.4 Mbit/s) as a slave. The

slave function is able to wake up the device from deep sleep and power down

modes.



Digital peripherals:



DMA controller with 22 channels and 20 programmable triggers, able to access all

memories and DMA-capable peripherals.

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