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LPC5410X датащи(PDF) 41 Page - NXP Semiconductors |
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LPC5410X датащи(HTML) 41 Page - NXP Semiconductors |
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41 / 95 page ![]() LPC5410x All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 2.11 — 19 September 2019 41 of 95 NXP Semiconductors LPC5410x 32-bit ARM Cortex-M4/M0+ microcontroller 10. Static characteristics 10.1 General operating conditions [1] The VDD voltage must be equal or lower than the voltage level on VDDA. [2] The Vrefp voltage must not exceed the voltage level on VDDA. 10.2 CoreMark data [1] Clock source 12 MHz IRC. PLL disabled. Table 9. General operating conditions Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit fclk clock frequency internal CPU/system clock - - 150 MHz VDD supply voltage (core and external rail) 1.62 - 3.6 V VDDA analog supply voltage [1] 1.62 - 3.6 V Vrefp ADC positive reference voltage VDDA 2 V [2] 2.0 - VDDA V VDDA < 2 V VDDA -VDDA V RTC oscillator pins Vi(rtcx) 32 kHz oscillator input voltage on pin RTCXIN 0.5 - +3.6 V Vo(rtcx) 32 kHz oscillator output voltage on pin RTCXOUT 0.5 - +3.6 V Table 10. CoreMark score Tamb = 25C, VDD = 3.3V Parameter Conditions Typ Unit ARM Cortex-M4 in active mode; ARM Cortex-M0+ in sleep mode CoreMark score CoreMark code executed from SRAM; CCLK = 12 MHz [1][3][4][5] 2.6 (Iterations/s) / MHz CCLK = 48 MHz [2][3][4][5] 2.6 (Iterations/s) / MHz CCLK = 84 MHz [2][3][4][5] 2.6 (Iterations/s) / MHz CCLK = 100 MHz [2][3][4][5] 2.6 (Iterations/s) / MHz CCLK = 150 MHz [2][3][4][5] 2.6 (Iterations/s) / MHz CoreMark score CoreMark code executed from flash; CCLK = 12 MHz; 1 system clock flash access time. [1][3][4][6] 2.6 (Iterations/s) / MHz CCLK = 48 MHz; 3 system clock flash access time. [2][3][4][6] 2.4 (Iterations/s) / MHz CCLK = 84 MHz; 5 system clock flash access time. [2][3][4][6] 2.3 (Iterations/s) / MHz CCLK = 100 MHz; 6 system clock flash access time. [2][3][4][6] 2.2 (Iterations/s) / MHz CCLK = 150 MHz; 7 system clock flash access time. [2][3][4][6] 1.94 (Iterations/s) / MHz |
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