TLE75620-EST datasheet(19/81 Pages) INFINEON

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Datasheet

Rev. 1.0

2017-11-23

TLE75620-EST

SPIDER+ 12V

Power Supply

The TLE75620-EST is supplied by two supply voltages:

• VS (analog supply voltage used also for the logic and as drain for channels 0 and 1)

• VDD (digital supply voltage)

The VS supply line is connected to a battery feed and used, in combination with VDD supply, for the driving

circuitry of the power stages. In situations where VS voltage drops below VDD voltage (for instance during

cranking events down to 3.0 V), an increased current consumption may be observed at VDD pin.

VS and VDD supply voltages have an undervoltage detection circuit, which prevents the activation of the

associated function in case the measured voltage is below the undervoltage threshold. More in detail:

• An undervoltage on both VS and VDD supply voltages prevents the activation of the power stages and any

SPI communication (the SPI registers are reset)

• An undervoltage on VDD supply prevents any SPI communication. SPI read/write registers are reset to

default values.

• An undervoltage on VS supply forces the TLE75620-EST to drain all needed current for the logic from VDD

supply. All channels are disabled, and are enabled again as soon as VS ≥ VS(OP).

Figure 11 shows a basic concept drawing of the interaction between supply pins VS and VDD, the output stage

drivers and SO supply line.

Figure 11 TLE75620-EST Internal Power Supply concept

When 3.0 V ≤ VS ≤ VDD - VSDIFF TLE75620-EST operates in “Cranking Operative Range” (COR). In this condition the

current consumption from VDD pin increases while it decreases from VS pin where the total current

consumption remains within the specified limits. Figure 12 shows the voltage levels at VS pin where the

device goes in and out of COR. During the transition to and from COR operative region, IVS and IVDD change

between values defined for normal operation and for COR operation. The sum of both current remains within

limits specified in “Overall current consumption” section (see Table 8).

SupplyConcept_620.emf

VDD

IVS

IVDD

VREG

SPI

UVR

VDD

UVR

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