TLE75620-EST datasheet(45/81 Pages) INFINEON

45 / 81 page

Datasheet

Rev. 1.0

2017-11-23

TLE75620-EST

SPIDER+ 12V

Protection Functions

be switched ON after clearing the protection latch by setting the corresponding HWCR_OCL.OUTn bit to “1”.

This bit is set back to “0” internally after de-latching the channel.

8.3

Over Temperature and Over Load Protection in Limp Home mode

When TLE75620-EST is in Limp Home mode, channels 2 and 3 can be switched ON using the input pins. In case

of Over Load, Short Circuit or Over Temperature the channels switch OFF. If the input pins remain “high”, the

channels restart with the following timings:

• 10 ms (first 8 retries)

•20 ms (following 8 retries)

•40 ms (following 8 retries)

• 80 ms (as long as the input pin remains “high” and the error is still present)

If at any time the input pin is set to “low” for longer than 2*tSYNC, the restart timer is reset. At the next channel

activation while in Limp Home mode the timer starts from 10 ms again. See Figure 23 for details. Over Load

current thresholds behave as described in Chapter 8.1.

Figure 23 Restart timer in Limp Home mode

8.4

Reverse Polarity Protection

In Reverse Polarity (also known as Reverse Battery) condition, power dissipation is caused by the intrinsic

body diode of each DMOS channel (for auto-configurable channels used as Low-Side switches), while High-

Side channels and auto-configurable channels used as High-Side switches have Reversave™ functionality.

Each ESD diode of the logic and supply pins contributes to total power dissipation. Channels with Reversave™

functionality are switched ON almost with the same RDS(ON) (see parameter RDS(REV)). The reverse current

through the channels has to be limited by the connected loads. The current through digital power supply VDD

and input pins has to be limited as well (please refer to the Absolute Maximum Ratings listed on Chapter 4.1).

Note:

No protection mechanism like temperature protection or current limitation is active during reverse

polarity.

8.5

Over Voltage Protection

In the case of supply voltages between VS(SC) and VS(LD) the output transistors are still operational and follow

the input pins or the OUT register.

In addition to the output clamp for inductive loads as described in Chapter 7.1.2, there is a clamp mechanism

available for over voltage protection for the logic and all channels, monitoring the voltage between VS and

GND pins (VS(AZ)).

IN0

IN1

IL2

LHrestart.emf

tRETRY0(LH)

10 ms

tRETRY1(LH)

20 ms

tRETRY2(LH)

40 ms

tRETRY3(LH)

80 ms

tRETRY0(LH)

10 ms

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