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TLE75620-EST датащи(PDF) 60 Page - Infineon Technologies AG

номер детали TLE75620-EST
подробное описание детали  SPIDER 12V SPI Driver for Enhanced Relay Control
PDF  81 Pages
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производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TLE75620-EST датащи(HTML) 60 Page - Infineon Technologies AG

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Datasheet
60
Rev. 1.0
2017-11-23
TLE75620-EST
SPIDER+ 12V
Serial Peripheral Interface (SPI)
Transfer delay time (rising CSN to
falling CSN)
tCSN(td)
250
–
–
ns
1)
VDD = 4.5 V or VS
> 7 V
P_10.4.19
Output enable time (falling CSN to
SO valid)
tSO(en)
–
–
200
ns
1)
VDD = 4.5 V or VS
> 7 V
CL = 20 pF at SO
pin
P_10.4.20
Output disable time (rising CSN to
SO tristate)
tSO(dis)
–
–
200
ns
1)
VDD = 4.5 V or VS
> 7 V
CL = 20 pF at SO
pin
P_10.4.21
Serial clock frequency
fSCLK
––
5
MHz 1)
VDD = 4.5 V or VS
> 7 V
P_10.4.22
Serial clock period
tSCLK(P)
200
–
–
ns
1)
VDD = 4.5 V or VS
> 7 V
P_10.4.23
Serial clock “high” time
tSCLK(H)
75
–
–
ns
1)
VDD = 4.5 V or VS
> 7 V
P_10.4.24
Serial clock “low” time
tSCLK(L)
75
–
–
ns
1)
VDD = 4.5 V or VS
> 7 V
P_10.4.25
Data setup time (required time SI
to falling SCLK)
tSI(su)
20
–
–
ns
1)
VDD = 4.5 V or VS
> 7 V
P_10.4.26
Data hold time (falling SCLK to SI) tSI(h)
20
–
–
ns
1)
VDD = 4.5 V or VS
> 7 V
P_10.4.27
Output data valid time with
capacitive load
tSO(v)
–
–
100
ns
1)
VDD = 4.5 V or VS
> 7 V
CL = 20 pF at SO
pin
P_10.4.28
Enable lead time (falling CSN to
rising SCLK)
tCSN(lead) 1–
–
μs
1)
VDD = VS = 3.0 V
P_10.4.29
Enable lag time (falling SCLK to
rising CSN)
tCSN(lag)
1–
–
μs
1)
VDD = VS = 3.0 V
P_10.4.30
Transfer delay time (rising CSN to
falling CSN)
tCSN(td)
1.25
–
–
μs
1)
VDD = VS = 3.0 V
P_10.4.31
Table 13
Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ.
Max.



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