TLE75620-EST datasheet(38/81 Pages) INFINEON

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Datasheet

Rev. 1.0

2017-11-23

TLE75620-EST

SPIDER+ 12V

Power Stages

For each PWM generator 4 parameters can be set:

• duty cycle (bits PWM_CR0.DC for PWM Generator 0)

– 8 bits are available to achieve 0.39% duty cycle resolution

– when the micro-controller programs a new duty cycle, the PWM generator waits until the previous cycle

is completed before using the new duty cycle (this happens also when the duty cycle is either 0% or

100% - the new duty cycle is taken with the next PWM cycle)

– the maximum duty cycle achievable is 99.61% (PWM_CR0.DC set to “11111111B”). It is possible to

achieve 100% by setting PWM_CR0.FREQ to “11B”

•frequency (bits PWM_CR0.FREQ for PWM Generator 0)

– with 2 bits is possible to select the divider for fINT to achieve the needed duty cycle

–00B = fINT / 1024 (when fINT = 102.4 kHz the corresponding PWM frequency is 100 Hz)

–01B = fINT / 512 (corresponding to 200 Hz)

–10B = fINT / 256 (corresponding to 400 Hz)

• channel output control and mapping registers PWM_OUT and PWM_MAP)

– any channel can be mapped to each PWM Generator

– together with 2 parallel input it is possible to have 4 independent PWM groups of channels with low

effort from the point of view of micro-controller resources and SPI data traffic

Figure 20 expands the concept shown in Figure 10 adding the PWM Generators.

Table 9

HWCR_PWM.ADJ coefficients overview

bit content

absolute delta to fINT

relative delta between steps

0000B

(reserved)

0001B

-37.2%

-5.2%

0010B

-31.9%

-5.1%

0011B

-26.9%

-5.9%

0100B

-21.0%

-5.5%

0101B

-15.5%

-4.6%

0110B

-10.9%

-5.1%

0111B

-5.8%

1000B

––

1001B

+4.3%

1010B

+8.9%

+4.6%

1011B

+14.0%

+5.1%

1100B

+19.5%

+5.6%

1101B

+25.6%

+6.1%

1110B

+32.4%

+6.8%

1111B

+40.0%

+7.6%

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