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TLE75620-EST датащи(PDF) 67 Page - Infineon Technologies AG |
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TLE75620-EST датащи(HTML) 67 Page - Infineon Technologies AG |
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67 / 81 page ![]() Datasheet 67 Rev. 1.0 2017-11-23 TLE75620-EST SPIDER+ 12V Serial Peripheral Interface (SPI) 10.6.2 Register structure The register banks the digital part have following structure: Table 18 summarizes the available registers with their addresing space and size Table 16 Register structure - all registers (with the exclusion of PWM_CR0 and PWM_CR1) 15 14 13 12 11 10 987654321 0 Default r = 0 w = 1 r = 1 w = 0 ADDR0 ADDR1 DATA XXXXH Table 17 Register structure - PWM_CR0 and PWM_CR1 15 14 13 12 11 10 9876543210 Default r = 0 w = 1 r = 1 w = 0 ADDR0 DATA XXXXH Table 18 Register addressing space Register name ADDR0 ADDR1 Size Type Purpose OUT n = 7 to 0 0000B 00B nr/w Power output control register bits OUT.OUTn 0B (default) Output is OFF 1B Output is ON BIM 0000B 01B 8r/w Bulb Inrush Mode bits BIM.OUTn 0B (default) Output latches OFF in case of errors 1B Output restarts automatically in case of errors MAPIN0 n = 7 to 0 0001B 00B nr/w Input Mapping (Input Pin 0) bits MAPIN0.OUTn 0B (default) The output is not connected to the input pin 1B The output is connected to the input pin Note: Channel 2 has the corresponding bit set to “1” by default |
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