AT21CS01 datasheet(16/47 Pages) MICROCHIP

16 / 47 page

Note: The interruption of protocol must not occur during a write sequence immediately after a logic ‘0’

“ACK” response when sending data to be written to the device. In this case, the interruption will be

interpreted as a Stop condition and will cause an internal write cycle to begin. The device will be busy for

tWR time and will not respond to any commands.

Note: For systems that cannot accurately monitor the location of interrupts, it is recommended to ensure

that a minimum interruption time be observed consistent with the longest busy operation of the device

(tWR). Communicating with the device while it is in an internal write cycle by the master driving SI/O low

could cause the byte(s) being written to become corrupted and must be avoided. The behavior of the

device during a write cycle is described in more detail in Device Behavior During Internal Write Cycle.

If the sequence is interrupted for longer than the maximum tBIT, the master must wait at least the

minimum tHTSS before continuing. By waiting the minimum tHTSS time, a new Start condition is created

and the device is ready to receive a new command. It is recommended that the master start over and

repeat the transaction that was interrupted midstream.

3.1.3.4

Data Output Bit Frame

A data output bit frame is used when the master is to receive communication back from the

AT21CS01/11. Data output bit frames are used when reading any data out as well as any ACK or NACK

responses from the device. Just as in the input bit frame, the master initiates the sequence by driving the

SI/O line below the VIL threshold which engages the AT21CS01/11 internal timing generation circuit.

Within the output bit frame is the critical timing parameter tRD, which is defined as the amount of time the

master must continue to drive the SI/O line low after crossing the below VIL threshold to request a data bit

back from the AT21CS01/11. Once the tRD duration has expired, the master must release the SI/O line.

If the AT21CS01/11 is responding with a logic ‘0’ (for either a ‘0’ data bit or an ACK response), it will begin

to pull the SI/O line low concurrently during the tRD window and continue to hold it low for a duration of

tHLD0, after which it will release the line to be pulled back up to VPUP (see Figure 3-6). Thus, when the

master samples SI/O within the tMRS window, it will see a voltage less than VIL and decode this event as a

logic ’0’. By definition, the tHLD0 time is longer than the tMRS time and therefore, the master is ensured to

sample while the AT21CS01/11 is still driving the SI/O line low.

Figure 3-6. Logic 0 Data Output Bit Frame Waveform

AT21CS01 [DATASHEET]

Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015

3.1.3.4 Data Output Bit Frame

A data output Bit Frame is used when the Master is to receive communication back from the AT21CS01. Data

output Bit Frames are used when reading any data out as well as any ACK or NACK responses from the device.

Just as in the input Bit Frame, the Master initiates the sequence by driving the SI/O line below the VIL threshold

which engages the AT21CS01’s internal timing generation circuit.

Within the output Bit Frame is the critical timing parameter tRD, which is defined as the amount of time the

Master must continue to drive the SI/O line low after crossing the below VIL threshold to request a data bit back

from the AT21CS01. Once the tRD duration has expired, the Master must release the SI/O line.

If the AT21CS01 is responding with a Logic 0 (for either a

‘0’ data bit or an ACK response), it will begin to pull

the SI/O line low concurrently during the tRD window and continue to hold it low for a duration of tHLD0, after

which it will release the line to be pulled back up to VPUP (see Figure 3-6). Thus, when the Master samples SI/O

within the tMRS window, it will see a voltage less than VIL and decode this event as a Logic 0. By definition, the

tHLD0 time is longer than the tMRS time and therefore the Master is guaranteed to sample while the AT21CS01 is

still driving the SI/O line low.

Figure 3-6.

Logic 0 Data Output Bit Frame Waveform

If the AT21CS01 intends to respond with a Logic 1 (for either a

‘1’ data bit or a NACK response), it will not drive

the SI/O line low at all. Once the Master releases the SI/O line after the maximum tRD has elapsed, the line will

be pulled up to VPUP. Thus when the Master samples the SI/O line within the tMRS window, it will detect a voltage

greater than VIH and decode this event as a Logic 1.

The data output Bit Frame is shown in greater detail below in Figure 3-7.

Figure 3-7.

Logic 1 Data Output Bit Frame Waveform

SI/O

VIL

VIH

tBIT

MASTER

PULL-UP RESISTOR

tMRS

tRCV

AT21CS01

Master

Sampling

Window

tRD

tHLD0

tPUP

SI/O

VIL

VIH

tBIT

MASTER

PULL-UP RESISTOR

tMRS

AT21CS01

Master

Sampling

Window

tRD

tPUP

Note: AT21CS01 will not drive the SI/O line during a Logic 1 output Bit Frame.

If the AT21CS01/11 intends to respond with a logic ‘1’ (for either a ‘1’ data bit or a NACK response), it will

not drive the SI/O line low at all. Once the master releases the SI/O line after the maximum tRD has

elapsed, the line will be pulled up to VPUP. Thus, when the master samples the SI/O line within the tMRS

window, it will detect a voltage greater than VIH and decode this event as a logic ‘1’.

The data output bit frame is shown in greater detail below in Figure 3-7.

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 16

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