AT21CS01 datasheet(18/47 Pages) MICROCHIP

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Device Addressing and I2C Protocol Emulation

Accessing the device requires a Start condition followed by an 8-bit device address word.

The AT21CS01/11 protocol sequence emulates what would be required for an I2C Serial EEPROM, with

the exception that the beginning four bits of the device address are used as an opcode for the different

commands and actions that the device can perform.

Since multiple slave devices can reside on the bus, each slave device must have its own unique address

so that the master can access each device independently. After the 4-bit opcode, the following three bits

of the device address byte are comprised of the slave address bits. The three slave address bits are

preprogrammed prior to shipment and are read-only. Obtaining devices with different slave address bit

values is done by purchasing a specific ordering code. Refer to Packaging Information for explanation of

which ordering code corresponds with a specific slave address value.

Following the three slave address bits is a Read/Write select bit where a logic ‘1’ indicates a read and a

logic ‘0’ indicates a write. Upon the successful comparison of the device address, the EEPROM will return

an ACK (logic ‘0’). If the 4-bit opcode is invalid or the three bits of slave address do not match what is

preprogrammed in the device, the device will not respond on the SI/O line and will return to a Standby

state.

Table 4-1. Device Address Byte

4-bit Opcode

Preprogrammed Slave Address Bits

Read/Write

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Refer to Available Opcodes

R/W

Following the device address byte, a memory address byte must be transmitted to the device

immediately. The memory address byte contains a 7-bit memory array address to specify which location

in the EEPROM to start reading or writing. Refer to Table 4-2 to review these bit positions.

Table 4-2. Memory Address Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Don’t Care

4.1

Memory Organization

The AT21CS01/11 internal memory array is partitioned into two regions. The main 1-Kbit EEPROM is

organized as 16 pages of eight bytes each. The Security register is 256 bits in length, organized as four

pages of eight bytes each. The lower two pages of the Security register are read-only and have a

factory

‑programmed, 64‑bit serial number that is unique across all AT21CS series Serial EEPROMs. The

upper two pages of the Security register are user-programmable and can be subsequently locked (see

Locking the Security Register).

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 18

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