AT21CS01 datasheet(24/47 Pages) MICROCHIP

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Following receipt of the data byte, the EEPROM will respond with an ACK and the master can send up to

an additional seven bytes if desired. The EEPROM will respond with an ACK after each data byte is

successfully received. Once all of the data bytes have been sent, the device requires a Stop condition to

begin the write cycle. However, since a Stop condition is defined as a null bit frame with SI/O pulled high,

the master does not need to drive the SI/O line to accomplish this. After the Stop condition is complete,

the EEPROM will enter an internally self-timed write cycle, which will complete within a time of tWR, while

the data is being programmed into the nonvolatile EEPROM. The SI/O pin must be pulled high via the

external pull-up resistor during the entire tWR cycle. Figure 6-3 is included below as an example of a byte

write operation in the Security register.

Figure 6-3. Byte Write in the Security Register

SI/O

MSB

ACK

by Slave

1 A2 A1 A0 0

Device Address

MSB

1 A3 A2 A1 A0

MSB

Data In Byte

ACK

by Slave

ACK

by Slave

Stop Condition

by Master

Start Condition

by Master

Security Register Address

Note:

x = Don’t Care values in the place of A7

‑A5 as these bits falls outside the addressable range of the

Security register.

Any attempt to interrupt the internal write cycle by driving the SI/O line low may cause the byte

being programmed to be corrupted. Other memory locations within the memory array will not be

affected. Note Device Behavior During Internal Write Cycle for the behavior of the device while the

write cycle is in progress. If the master must interrupt a write operation, the SI/O line must be driven

low for tDSCHG as noted in Interrupting the Device during an Active Operation.

6.5

Locking the Security Register

The Lock command is an irreversible sequence that will permanently prevent all future writing to the

upper 16 bytes of the Security register on the AT21CS01/11. Once the Lock command has been

executed, the entire 32-byte Security register becomes read-only. Once the Security register has been

locked, it is not possible to unlock it.

The Lock command protocol emulates a byte write operation to the Security register, however, the

opcode 0010b (2h) is required along with the A7 through A4 bits of the memory address being set to

0110b (6h). The remaining bits of the memory address, as well as the data byte are "don’t care" bits.

Even though these bits are "don’t cares", they still must be transmitted to the device. An ACK response to

the memory address and data byte indicates the Security register is not currently locked. A NACK

response indicates the Security register is already locked. Refer to Figure 6-5 for details about

determining the Lock status of the Security register.

The sequence completes with a Stop condition to initiate a self-timed internal write cycle. If a Stop

condition is sent at any other time, the Lock operation is aborted. Since a Stop condition is defined as a

null bit frame with SI/O pulled high, the master does not need to drive the SI/O line to accomplish this.

Upon completion of the write cycle, (taking a time of tWR), the Lock operation is complete and the Security

Note:

Any attempt to drive the SI/O line low during the tWR time period may cause the Lock operation to

not complete successfully, and must be avoided.

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 24

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