AT21CS01 datasheet(25/47 Pages) MICROCHIP

25 / 47 page

Figure 6-4. Lock Command

SI/O

MSB

ACK

by Slave

0 A2 A1 A0 0

Device Address

MSB

Lock Security Register Address

MSB

Data In Byte

ACK

by Slave

ACK

by Slave

Stop Condition

by Master

Start Condition

by Master

6.5.1

Device Response to a Write Command on a Locked Device

A locked device will respond differently to a Write command to the Security register compared to a device

that has not been locked. Writing to the Security register is accomplished by sending a Start condition

followed by a device address byte with the opcode of 1011b (Bh), the appropriate slave address

combination, and the Read/Write bit set as a logic ‘0’. Both a locked device and a device that has not

been locked will return an ACK. Next, the 8-bit word address is sent and again, both devices will return an

ACK. However, upon sending the data input byte, a device that has already been locked will return a

NACK and be immediately ready to accept a new command, whereas a device that has not been locked

will return an ACK to the data input byte as per normal operation for a Write command as described in

Write Operations.

6.5.2

Check Lock Command

The Check Lock command follows the same sequence as the Lock command (including 0110b in the A7

through A4 bits of the memory address byte) with the exception that only the device address byte and

memory address byte need to be transmitted to the device. An ACK response to the memory address

byte indicates that the lock has not been set while a NACK response indicates that the lock has been set.

If the lock has already been enabled, it cannot be reversed. The Check Lock command is completed by

the master sending a Stop bit to the device (defined as a null bit frame).

Figure 6-5. Check Lock Command

SI/O

MSB

ACK

by Slave

0 A2 A1 A0 0

Device Address

MSB

Lock Security Register Address

ACK by Slave

if Unlocked

NACK by Slave

if Locked

Stop Condition

by Master

Start Condition

by Master

6.6

Setting the Device Speed

The AT21CS01 can be set to Standard Speed mode (15.4 kbps maximum) or High-Speed mode

(125 kbps maximum) through a software sequence. Upon executing a Reset and Discovery Response

sequence (see Device Reset/Power-up and Discovery Response), the device will default to High-Speed

mode. The AT21CS11 does not have Standard Speed mode.

6.6.1

Standard Speed Mode (AT21CS01)

The AT21CS01 can be set to Standard Speed mode or checked to see whether or not it is in Standard

Speed mode with the use of the Dh opcode. This transaction only requires eight bits.

To set the device to Standard Speed mode, the master must send a Start condition, followed by the

device address byte with the opcode of 1101b (Dh) specified, along with the appropriate slave address

combination and the Read/Write bit set to a logic ‘0’. The device will return an ACK (logic ‘0’) and will be

immediately ready to receive commands for standard speed operation.

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 25

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