AT21CS01 datasheet(27/47 Pages) MICROCHIP

27 / 47 page

Read Operations

Read operations are initiated in a similar way as write operations with the exception that the Read/Write

select bit in the device address byte must be set to a logic ‘1’. There are multiple read operations

supported by the device:

•

Current Address Read within the EEPROM

•

Random Read within the EEPROM

•

Sequential Read within the EEPROM

•

Read from the Security Register

•

Manufacturer ID Read

Note:

The AT21CS01/11 contains a single, shared-memory Address Pointer that maintains the

address of the next byte in the EEPROM or Security register to be accessed. For example, if

the last byte read or written was memory location 0Dh of the EEPROM, then the Address

Pointer will be pointing to memory location 0Eh of the EEPROM. As such, when changing

from a read in one region to the other, the first read operation in the new region should begin

with a random read instead of a current address read to ensure the Address Pointer is set to

a known value within the desired region.

If the end of the EEPROM or the Security register is reached, then the Address Pointer will “roll over”

back to the beginning (address 00h) of that region. The Address Pointer retains its value between

operations as long as the pull-up voltage on the SI/O pin is maintained or as long as the device has not

been reset.

7.1

Current Address Read within the EEPROM

The internal Address Pointer must be pointing to a memory location within the EEPROM in order to

perform a current address read from the EEPROM. To initiate the operation, the master must send a Start

condition, followed by the device address byte with the opcode of 1010b (Ah) specified, along with the

appropriate slave address combination and the Read/Write bit set to a logic ‘1’. After the device address

byte has been sent, the AT21CS01/11 will return an ACK (logic ‘0’).

Following the ACK, the device is ready to output one byte (eight bits) of data. The master initiates the all

bits of data by driving the SI/O line low to start. The AT21CS01/11 will hold the line low after the master

releases it to indicate a logic ‘0’. If the data is logic ‘1’, the AT21CS01/11 will not hold the SI/O line low at

all, causing it to be pulled high by the pull-up resistor once the master releases it. This sequence repeats

for eight bits.

After the master has read the first data byte and no further data is desired, the master must return a

NACK (logic ‘1’) response to end the read operation and return the device to the Standby mode. Figure

7-1 depicts this sequence.

If the master would like the subsequent byte, it would return an ACK (logic ‘0’) and the device will be

ready output the next byte in the memory array. Refer to Sequential Read within the EEPROM for details

about continuing to read beyond one byte.

Note:

If the last operation to the device was an access to the Security register, then a random read should

be performed to ensure that the Address Pointer is set to a known memory location within the

EEPROM.

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 27

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