AT21CS01 datasheet(12/47 Pages) MICROCHIP

12 / 47 page

Device Operation and Communication

The AT21CS01/11 operates as a slave device and utilizes a single

‑wire digital serial interface to

communicate with a host controller, commonly referred to as the bus master. The master controls all read

and write operations to the slave devices on the serial bus. The device has two speeds of operation,

Standard Speed mode (AT21CS01) and High-Speed mode (AT21CS01 and AT21CS11).

The device utilizes an 8-bit data structure. Data is transferred to and from the device via the single

‑wire

serial interface using the Serial Input/Output (SI/O) pin. Power to the device is also provided via the SI/O

pin, thus only the SI/O pin and the GND pin are required for device operation. Data sent to the device

over the single

‑wire bus is interpreted by the state of the SI/O pin during specific time intervals or slots.

Each time slot is referred to as a bit frame and lasts tBIT in duration. The master initiates all bit frames by

driving the SI/O line low. All commands and data information are transferred with the Most Significant bit

(MSb) first.

The software sequence sent to the device is an emulation of what would be sent to an I2C Serial

EEPROM with the exception that typical 4-bit device type identifier of 1010b in the device address is

replaced by a 4-bit opcode. The device has been architected in this way to allow for rapid deployment

and significant reuse of existing I2C firmware. For more details about the way the device operates, refer

to Device Addressing and I2C Protocol Emulation .

During bus communication, one data bit is transmitted in every bit frame, and after eight bits (one byte) of

data has been transferred, the receiving device must respond with either an acknowledge (ACK) or a

no-acknowledge (NACK) response bit during a ninth bit window. There are no unused clock cycles during

any read or write operation, so there must not be any interruptions or breaks in the data stream during

each data byte transfer and ACK or NACK clock cycle. In the event where an unavoidable system

interrupt is required, refer to the requirements outlined in Communication Interruptions.

3.1

Single-Wire Bus Transactions

Types of data transmitted over the SI/O line:

•

Reset and Discovery Response

•

Logic ‘0’ or Acknowledge (ACK)

•

Logic ‘1’ or No Acknowledge (NACK)

•

Start Condition

•

Stop Condition

The Reset and Discovery Response is not considered to be part of the data stream to the device,

whereas the remaining four transactions are all required in order to send data to and receive data from

the device. The difference between the different types of data stream transactions is the duration that

SI/O is driven low within the bit frame.

3.1.1

Device Reset/Power-up and Discovery Response

3.1.1.1

Resetting the Device

A Reset and Discovery Response sequence is used by the master to reset the device as well as to

perform a general bus call to determine if any devices are present on the bus.

To begin the Reset portion of the sequence, the master must drive SI/O low for a minimum time. If the

device is not currently busy with other operations, the master can drive SI/O low for a time of tRESET. The

length of tRESET differs for Standard Speed mode and for High-Speed mode.

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 12

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