AT21CS01 datasheet(34/47 Pages) MICROCHIP

34 / 47 page

Figure 8-2. Writing to a ROM Zone Register

SI/O

MSB

ACK

by Slave

1 A2 A1 A0 0

Device Address

MSB

0 A3 A2 A1 A0

ROM Zone Register Address

MSB

Data In Byte (FFh)

ACK

by Slave

ACK

by Slave

Stop Condition

by Master

Start Condition

by Master

Note:

Any attempt to interrupt the internal write cycle by driving the SI/O line low may cause the register

being programmed to become corrupted. Note Device Behavior During Internal Write Cycle for the

behavior of the device while a write cycle is in progress. If the master must interrupt a write

operation, the SI/O line must be driven low for tDSCHG as noted in Interrupting the Device during an

Active Operation.

8.2.3

Freeze ROM Zone Registers

The current ROM Zone state can be frozen so that no further modifications to the ROM Zone registers

can be made. Once frozen, this event cannot be reversed.

To freeze the state of the ROM Zone registers, the master must send a Start condition, followed by the

device address byte with the opcode of 0001b (1h) specified, along with the appropriate slave address

combination and the Read/Write bit set to a logic ‘0’. The device will return either an ACK (logic ‘0’)

response if the ROM Zone registers have not been previously frozen or a NACK (logic ‘1’) response if the

registers have already been frozen.

If the AT21CS01/11 returns an ACK, the master must send a fixed arbitrary address byte value of 55h, to

which the device will return an ACK (logic ‘0’). Following the 55h address byte, a data byte of AAh must

be sent by the master. The device will ACK after the AAh data byte. If an address byte other than 55h or

a data byte other than AAh is sent, the device will NACK (logic ‘1’) and the freeze operation will not be

performed.

To complete the Freeze ROM Zone register sequence, a Stop condition is required. If a Stop condition is

sent at any other point in this sequence, the operation is aborted. Since a Stop condition is defined as a

null bit frame with SI/O pulled high, the master does not need to drive the SI/O line to accomplish this.

After the Stop condition is complete, the internally self-timed write cycle will begin.The SI/O pin must be

pulled high via the external pull-up resistor during the entire tWR cycle.

Figure 8-3. Freezing the ROM Zone Registers

SI/O

MSB

ACK

by Slave

1 A2 A1 A0 0

Device Address

MSB

Fixed Abitrary Address (55h)

MSB

Data In Byte (AAh)

ACK

by Slave

ACK

by Slave

Stop Condition

by Master

Start Condition

by Master

Note:

Any attempt to drive the SI/O line low during the tWR time period may cause the Freeze operation to

not complete successfully, and must be avoided.

8.3

Device Response to a Write Command Within an Enabled ROM Zone

The AT21CS01/11 will respond differently to a Write command in a memory zone that has been set to

ROM compared to Write command in a memory zone that has not been set to ROM. Writing to the

EEPROM is accomplished by sending a Start condition followed by a device address byte with the

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 34

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