AT21CS01 datasheet(23/47 Pages) MICROCHIP

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6.3

Page Write

A page write operation allows up to eight bytes to be written in the same write cycle, provided all bytes

are in the same row (address bits A6 through A3 are the same) of the memory array. Partial page writes

of less than eight bytes are allowed.

A page write is initiated the same way as a byte write, but the bus master does not send a Stop condition

after the first data byte is clocked in. Instead, after the EEPROM acknowledges receipt of the first data

byte, the bus master can transmit up to an additional seven data bytes.

The EEPROM will respond with an ACK after each data byte is received. Once all data bytes have been

sent, the device requires a Stop condition to begin the write cycle. However, since a Stop condition is

defined as a null bit frame with SI/O pulled high, the master does not need to drive the SI/O line to

accomplish this. If a Stop condition is sent at any other time, the write operation is aborted. After the Stop

condition is complete, the internally self-timed write cycle will begin.The SI/O pin must be pulled high via

the external pull-up resistor during the entire tWR cycle. Thus, in a multi

‑slave environment,

communication to other single-wire devices on the bus should not be attempted while any devices are in

an internal write cycle.

The lower three bits of the memory address are internally incremented following the receipt of each data

byte. The higher order address bits are not incremented, and the device retains the memory page

location. Page write operations are limited to writing bytes within a single physical page, regardless of the

number of bytes actually being written. When the incremented word address reaches the page boundary,

the address counter will “roll over” to the beginning of the same page. Nevertheless, creating a roll over

event should be avoided as previously loaded data in the page could become unintentionally altered.

After the maximum tWR time has elapsed, the master may begin a new bus transaction.

Note:

Any attempt to interrupt the internal write cycle by driving the SI/O line low may cause the bytes

being programmed to be corrupted. Other memory locations within the memory array will not be

affected. Note Device Behavior During Internal Write Cycle for the behavior of the device while the

write cycle is in progress. If the master must interrupt a write operation, the SI/O line must be driven

low for tDSCHG as noted in Interrupting the Device during an Active Operation.

Figure 6-2. Page Write

SI/O

MSB

ACK

by Slave

0 A2 A1 A0 0

Device Address

MSB

x A6 A5 A4 A3 A2 A1 A0

Memory Address

MSB

Data In Byte (1)

Data In Byte (8)

ACK

by Slave

ACK

by Slave

ACK

by Slave

Stop Condition

by Master

Start Condition

by Master

Note:

x = Don’t Care bit in the place of A7 as this bit falls outside the 1-Kbit addressable range.

6.4

Writing to the Security Register

The Security register supports bytes writes, page writes, and partial page writes in the upper 16 bytes

(upper two pages of eight bytes each) of the region. Page writes and partial page writes in the Security

EEPROM.

Upon receipt of the proper device address byte (with opcode of Bh specified) and memory address byte,

the EEPROM will send a logic ‘0’ to signify an ACK. The device will then be ready to receive the first data

byte.

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 23

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