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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F479 датащи(PDF) 37 Page - STMicroelectronics |
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STM32F479 датащи(HTML) 37 Page - STMicroelectronics |
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37 / 91 page  DocID029237 Rev 2 37/91 AN4861 Creating a graphical application with LTDC 89 Table 10 lists the maximal supported pixel clock at system level for the STM32F4x9 line and Table 11 lists the maximal supported pixel clock at system level for the STM32F7x6, STM32F7x7, STM32F7x8 and STM32F7x9 lines in the following conditions: • For the STM32F4x9 line the system clock HCLK is running @ 180 MHz and the SDRAM is @ 90 MHz. • For the STM32F7x6, STM32F7x7, STM32F7x8 and STM32F7x9 lines the system clock HCLK is running @ 200 MHz and the SDRAM is @ 100 MHz. • One or two AHB masters concurrent access to SDRAM (LTDC or LTDC+DMA2D). • The SDRAM bus width is 16-bit or 32-bit. • Either only one LTDC layer or two layers are used. • The LTDC layer color depth is 8 bpp, 16 bpp, 24 bpp or 32 bpp. Table 10. STM32F4x9 with HCLK @ 180 MHz and SDRAM @ 90 MHz maximal supported pixel clock versus LTDC configuration and SDRAM bus width Used LTDC layers Color depth (bpp) Maximum pixel clock (MHz) LTDC LTDC + DMA2D SDRAM 16-bit SDRAM 32-bit SDRAM 16-bit SDRAM 32-bit 1 layer 32 38 67 22 35 24 51 83 30 47 16 76 83 45 70 8 8383 8383 2 layers 32/32 19 33 NA 18 32/24 2238 1321 32/16 2544 1525 32/8 3053 1930 24/24 2644 1524 24/16 3153 1830 24/8 3867 2338 16/16 3967 2237 16/8 5183 3150 8/8 7883 4674 |
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