STM32F479 datasheet(54/91 Pages) STMICROELECTRONICS

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Creating a graphical application with LTDC

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GPIOs configuration using STM32CubeMX tool

To connect a display panel to an STM32 MCU, the user should configure the GPIOs to be

used for interfacing.

Using the STM32CubeMX tool is a very simple, easy and rapid way to configure the LTDC

peripheral and its GPIOs since it allows to generate a project with a preconfigured LTDC.

Section Section 6.2.3: LTDC GPIOs configuration provides a guide on how to configure the

LTDC GPIOs.

Configuration of specific pins of a display module

Some display modules may need other signals to be fully functional. The user can use

GPIOs and some peripherals to control these signals.

An example of using GPIOs to control the display enable pin (LCD_DISP) on a display

panel is described in section Section 6.2.3: LTDC GPIOs configuration.

Enabling LTDC interrupts

To be able to use the LTDC interrupts, the user should enable the LTDC global interrupts on

the NVIC side. Then, each interrupt is enabled separately by enabling its corresponding

enable bit. The LTDC interrupt-enable bits are available in the LTDC_IER register described

in Table 7: LTDC interrupts summary.

Note:

The FIFO underrun and transfer error interrupts are enabled in the hal_ltdc driver

HAL_LTDC_Init() function

An example of enabling LTDC interrupts using STM32CubeMX is described in

Section 6.2.3: LTDC GPIOs configuration.

4.7.2

LTDC clocks and timings configuration

This section describes the steps needed to configure the LTDC clock and timings respecting

the display specifications. It also provides a configuration example for the ROCKTECH

(RK043FN48H) display embedded on the STM32F746G-DISCO board.

System clock configuration

It is recommended to use the highest system clock to get the best graphic performances.

This recommendation applies also for the external memory framebuffer. So if an external

memory is used for the framebuffer, the highest allowed clock speed should be used to get

the best memory bandwidth.

For instance for the STM32F4x9 microcontrollers the maximum system speed is 180 MHz,

so if an external SDRAM is connected to the FMC the maximum SDRAM clock is 90 MHz

(HCLK/2).

For the STM32F7 Series, the maximum system speed is 216 MHz but with this speed and

HCLK/2 prescaler the SDRAM speed exceeds the maximum allowed speed (see product”s

datasheet for more details). So to get the maximum SDRAM, it is recommended to

configure HCLK to 200 MHz, then the SDRAM speed is set to 100 MHz.

The clock configuration providing the highest performances is:

•

STM32F4x9 devices: HCLK @ 180 MHz and SDRAM @ 90 MHz.

•

STM32F7 Series: HCLK @ 200 MHz and SDRAM @ 100 MHz.

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