STM32F479 datasheet(51/91 Pages) STMICROELECTRONICS

номер детали	STM32F479

подробное описание детали	LCD-TFT display controller (LTDC) on STM32 MCUs

PDF	91 Pages

Scroll/Zoom	100%

производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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DocID029237 Rev 2

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AN4861

Creating a graphical application with LTDC

Figure 29. FMC SDRAM and NOR/PSRAM memory swap at default

system memory map (MPU disabled)

MPU and Cache policy configuration

The use of Cortex®-M7 cache allows to boost system and graphic performances. This

performance gain is especially seen when CPU is accessing external memories such as

SDRAM or Quad-SPI.

In a graphical application, when the CPU is used for framebuffer processing, it is

recommended to use the cache especially if the framebuffer is located in an external

memory like SDRAM or SRAM. In that case user should consider the following points when

using the cache:

•

MPU memory region cacheability

As previously illustrated in Figure 29, in the default system memory region MPU

attributes, some system memory regions are normal cacheable while others are device

non-cacheable.

When the CPU is used for framebuffer processing, the user should change the

framebuffer region MPU attribute to normal cacheable (or do an FMC swap, see

Figure 29).

STM32F479 датащи(PDF) 51 Page - STMicroelectronics