STM32F479 datasheet(49/91 Pages) STMICROELECTRONICS

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AN4861

Creating a graphical application with LTDC

performances and may lead to system errors (if the LTDC framebuffer is located in

external memory and/or if the Quad-SPI memory is used for graphics).

•

The Cortex®-M7 CPU embeds an L1-Cache (see Figure 10).

Some graphic issues may be encountered due to unsuitable cache settings; bad

graphic visual effects may occur if cache maintenance is not properly performed. If the

suitable cache maintenance method is not used, graphical performances may be

impacted.

4.6.1

Disable FMC bank1 if not used

After reset, the FMC bank1 is always enabled to allow boot into external memories. Since

the Cortex®-M7 is doing some speculations, it can generate a speculative read access to

the first FMC bank.

The default FMC configuration being very slow, this speculative access blocks the access to

the FMC by other AHB masters for a very long time, leading to underrun on the LTDC side.

To prevent this CPU speculative read accesses on the FMC bank1, it is recommended to

disable it when it is not used. This can be done by resetting the MBKEN Bit in FMC_BCR1

To disable the FMC Bank1, the user can use the following code:

/* Disabling FMC Bank1: After reset FMC_BCR1 = 0x000030DB

where MBKEN = 1b meaning that FMC_Bank1 is enabled

and MTYP[1:0]= 10 meaning that memory type is set to NOR Flash/OneNAND

Flash*/

FMC_Bank1->BTCR[0] = 0x000030D2;

For more details on FMC configuration refer to the relevant STM32 reference manual.

4.6.2

Configure the memory protection unit (MPU)

This section defines the STM32F7 Series system memory attributes and the basic MPU

concepts. It also describes how to configure the MPU in order to prevent graphical

performance issues related to the Cortex®-M7 speculative read accesses and cache

maintenance.

Note:

This section is only describing some necessary basic MPU concepts needed for

configuration. For further details on MPU and cache, refer to the following documents:

- AN4838 application note “Managing memory protection unit (MPU) in STM32 MCUs”

- AN4839 application note “Level 1 cache on STM32F7 Series”

- STM32F7 Series Cortex®-M7 processor programming manual (PM0253)

- ARM Cortex®-M7 technical reference manual.

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