STM32F479 datasheet(36/91 Pages) STMICROELECTRONICS

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Creating a graphical application with LTDC

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SDRAM but he extracted a pixel clock corresponding to a 32-bit SDRAM, which

would be a mistake).

The color framebuffer line width is not 64 bytes aligned (see Section 4.5.2:

Optimizing the LTDC framebuffer fetching from external memories (SDRAM or

SRAM).

For the STM32F7 Series, the MPU is not correctly configured to avoid Cortex®-M7

speculative read accesses to the SDRAM (see Section 4.6: Special

recommendations for Cortex®-M7 (STM32F7 Series)).

If the FIFO underrun is still set because there are more than two AHB masters

concurrent access to the external memory, the user should relax the memory

bandwidth using the below recommendations:

–

use only one LTDC Layer

–

use the largest possible memory bus width (use 32-bit instead of 16-bit or 8-bit

SDRAM/SRAM)

–

update the framebuffer content during the blanking period when the LTDC is not

fetching

–

use the highest possible system clock HCLK and the highest memory speed

(FMC_SDRAM/FMC_SRAM)

–

decrease the images color depth (BPP)

–

For more details on memory bandwidth optimization see Section 4.5: Graphic

performance optimization.

Note:

To evaluate the STM32's graphical capability in a specific hardware configuration, the user

can use the STM32 boards described in Table 17: STM32 reference boards with embedding

LTDC and featuring an on-board LCD-TFT panel.

Figure 22 shows a typical graphic hardware configuration where an external SDRAM is

connected to the FMC which is used for framebuffer. The SDRAM memory bandwidth

depends on the bus width and in the operating clock.

The SDRAM bus width can be 32-bit, 16-bit or 8-bit, while the operating clock depends on

the system clock HCLK and the configured prescaler (HCLK/2 or HCLK/3).

Figure 22. Typical graphic hardware configuration with external SDRAM

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