STM32F479 datasheet(52/91 Pages) STMICROELECTRONICS

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Creating a graphical application with LTDC

AN4861

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DocID029237 Rev 2

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Cache maintenance and data coherency: visual impact of WBWA without cache

maintenance operation

The data coherency issue is often encountered when performing framebuffer

processing using a Cortex®-M7 CPU with L1-cache enabled and a WBWA cache

policy. This issue occurs when multiple masters such as Cortex®-M7 and LTDC are

sharing the same region (framebuffer) and the cache maintenance is not performed.

When the CPU is processing the framebuffer (writes to framebuffer) and if the

framebuffer region has a write-back cache policy, the processed result (image to be

displayed) is not seen on the framebuffer (may be SRAM or SDRAM), and then it is not

displayed.

To avoid this issue, the user should use one of the following methods:

–

Configure the framebuffer region cache attribute to write-through (WT), in that

case each write operation is performed on the cache and on the framebuffer.

–

Configure the framebuffer region cache attribute to write back write allocate

(WBWA) and perform the cache maintenance by software.

Write-through is safer for data coherency but may impact graphic performances.

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Cache maintenance may impact graphic performances

The user should use the suitable cache policy matching his application. Each method

has its cons and pros. So the user should consider the following particularities for each

method:

–

Write-through: is very simple to manage (no need to perform cache maintenance

by software) and safer for data coherency but it generates a lot of single write

operations to the framebuffer which may impact LTDC accesses.

Note:

The user should also consider that cache maintenance may impact graphic performances

even when the CPU is not used for framebuffer processing. Thus, in some applications the

CPU is accessing to the external SDRAM or SRAM for purposes other than graphics with

cache enabled. In that case, cache maintenance may impact the LTDC accesses.

–

Write back write allocate: it is more suitable to use WBWA and software routine

and synchronize the cache maintenance operation with the LTDC during blanking.

This allows to create additional bandwidth on the framebuffer memory (SRAM or

SDRAM). The cache maintenance operation should be performed by software

after writing data to the framebuffer memory region; this is done by forcing a D-

cache clean operation using the CMSIS function SCB_CleanDCache(). So all the

dirty lines in the cache are written back to the framebuffer.

MPU configuration example

An example of MPU configuration is described in Section 6.2.7, showing how to set the

framebuffer MPU attribute when the CPU is used (with cache enabled) for graphical

operations. The described example is created for the STM32F746G-DISCO board hardware

configuration where the external SDRAM is used for framebuffer and the external QSPI

Flash memory is containing the graphic primitives.

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