STM32F479 datasheet(81/91 Pages) STMICROELECTRONICS

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LTDC application examples

6.2.6

FMC SDRAM configuration

The external SDRAM must be configured as it contains the LTDC framebuffer. To configure

the FMC_SDRAM and the SDRAM memory device mounted on the STM32746G-Discovery

board, the user can use either STM32CubeMX or use the existing BSP driver.

To configure the FMC_SDRAM using the BSP driver follow the steps described below:

Add the following files to the project: BSP stm32746g_discovery_sdram.c and

stm32746g_discovery_sdram.h. Include the stm32f7xx_hal_sdram.h in the main.c file.

Add the stm32f7xx_hal_sdram.c and stm32f7xx_ll_fmc.c HAL drivers to the project

Enable the SDRAM module in the stm32f7xx_hal_conf.h file by uncommenting the

SDRAM module definition. Include the stm32f7xx_hal_sdram.h file in the main.c file.

Call the BSP_SDRAM_Init() function in the main() function.

6.2.7

MPU and cache configuration

As illustrated in Section 4.6, the MPU attributes should be correctly configured in order to

prevent graphical performance issues related to the Cortex®-M7 speculative read accesses

and cache maintenance.

This section describes an example of MPU attribute configuration with respect to the

STM32F746G-DISCO board hardware configuration.

The MPU memory attributes can be easily configured with STM32CubeMX. A code example

of MPU configuration generated using STM32CubeMX is described at the end of this

section.

MPU configuration example: FMC_SDRAM

In this configuration example, the double framebuffer technique is used; the frontbuffer is

placed in the SDRAM bank1 while the backbuffer is placed in the SDRAM bank2 with

respect to the SDRAM bandwidth optimization described in Section 4.5.3: Optimizing the

LTDC framebuffer fetching from SDRAM.

The following MPU regions are created (FMC without sawp):

•

Region0: defines the SDRAM memory size 8 MByte

•

Region1: defines the frontbuffer 256 Kbyte (16 bpp x 480 x 272), it overlaps region0

•

Region2: defines the backbuffer 256 Kbyte (16 bpp x 480 x 272), it overlaps region0

Figure 52 illustrates the MPU configuration of the SDRAM region.

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