HD64F2145 datasheet(32/829 Pages) RENESAS

32 / 829 page

Rev. 2.0, 08/02, page xxx of xxxviii

Figure 23.12 Erase/Erase-Verify Flowchart................................................................................601

Figure 23.13 Memory Map in Programmer Mode ......................................................................604

Section 24 Masked ROM

Figure 24.1 Block Diagram of 128-Kbyte Masked ROM (HD6432161BV) ..............................607

Figure 24.2 Block Diagram of 64-Kbyte Masked ROM (HD6432160BV) ................................607

Section 25 Clock Pulse Generator

Figure 25.1 Block Diagram of Clock Pulse Generator................................................................609

Figure 25.2 Typical Connection to Crystal Resonator ................................................................610

Figure 25.3 Equivalent Circuit of Crystal Resonator ..................................................................610

Figure 25.4 Example of External Clock Input ............................................................................611

Figure 25.5 External Clock Input Timing ...................................................................................612

Figure 25.6 Timing of External Clock Output Stabilization Delay Time ...................................613

Figure 25.7 Subclock Input Timing ............................................................................................ 614

Figure 25.8 Processing for X1 and X2 Pins ................................................................................615

Figure 25.9 Note on Board Design of Oscillator Circuit Section................................................616

Section 26 Power-Down Modes

Figure 26.1 Mode Transition Diagram........................................................................................623

Figure 26.2 Medium-Speed Mode Timing..................................................................................626

Figure 26.3 Application Example in Software Standby Mode....................................................628

Figure 26.4 Hardware Standby Mode Timing.............................................................................629

Section 28 Electrical Characteristics

Figure 28.1 Darlington Pair Drive Circuit (Example).................................................................684

Figure 28.2 LED Drive Circuit (Example)..................................................................................685

Figure 28.3 Output Load Circuit .................................................................................................686

Figure 28.4 Connection of VCL Capacitor .................................................................................698

Figure 28.5 Connection of VCL Capacitor .................................................................................736

Figure 28.6 System Clock Timing ..............................................................................................736

Figure 28.7 Oscillation Settling Timing......................................................................................737

Figure 28.8 Oscillation Setting Timing (Exiting Software Standby Mode)................................737

Figure 28.9 Reset Input Timing ..................................................................................................738

Figure 28.10 Interrupt Input Timing ...........................................................................................738

Figure 28.11 Basic Bus Timing (Two-State Access) ..................................................................739

Figure 28.12 Basic Bus Timing (Three-State Access) ................................................................740

Figure 28.13 Basic Bus Timing (Three-State Access with One Wait State)...............................741

Figure 28.14 Burst ROM Access Timing (Two-State Access) ...................................................742

Figure 28.15 Burst ROM Access Timing (One-State Access) ....................................................742

Figure 28.16 I/O Port Input/Output Timing ................................................................................743

Figure 28.17 FRT Input/Output Timing......................................................................................743

Figure 28.18 FRT Clock Input Timing .......................................................................................744

Figure 28.19 8-Bit Timer Output Timing....................................................................................744

Figure 28.20 8-Bit Timer Clock Input Timing............................................................................744

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