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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD64F2145 датащи(PDF) 76 Page - Renesas Technology Corp |
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HD64F2145 датащи(HTML) 76 Page - Renesas Technology Corp |
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76 / 829 page  Rev. 2.0, 08/02, page 36 of 788 SP (ER7) Free area Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR does not affect operation in this LSI. Bit Bit Name Initial Value R/W Description 7 T 0 R/W Trace Bit Does not affect operation in this LSI. 6 to 3 — All 1 R Reserved These bits are always read as 1. 2 to 0 I2 I1 I0 All 1 R/W Interrupt Mask Bits 2 to 0 Do not affect operation in this LSI. 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. |
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