HD64F2145 datasheet(28/829 Pages) RENESAS

28 / 829 page

Rev. 2.0, 08/02, page xxvi of xxxviii

Figure 12.12 Timing of Input Capture Signal

(Input capture signal is input during TICRR and TICRF read)..............................288

Figure 12.13 Input Capture Signal Selection ..............................................................................289

Figure 12.14 Conflict between TCNT Write and Clear ..............................................................291

Figure 12.15 Conflict between TCNT Write and Increment.......................................................292

Figure 12.16 Conflict between TCOR Write and Compare-Match.............................................293

Section 13 Timer Connection

Figure 13.1 Block Diagram of Timer Connection ......................................................................298

Figure 13.2 Timing Chart for PWM Decoding ...........................................................................310

Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)................311

Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal) ................................311

Figure 13.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided

Waveform Periods....................................................................................................314

Figure 13.6 2fH Modification Timing Chart...............................................................................315

Figure 13.7 Fall Modification and IHI Synchronization Timing Chart.......................................317

Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart..................................................319

Figure 13.9 CBLANK Output Waveform Generation ................................................................322

Section 14 Watchdog Timer (WDT)

Figure 14.1 Block Diagram of WDT ..........................................................................................326

Figure 14.2 Watchdog Timer Mode (RST/

10, = 1) Operation .................................................333

Figure 14.3 Interval Timer Mode Operation ...............................................................................334

Figure 14.4 OVF Flag Set Timing .............................................................................................. 334

Figure 14.5 Output Timing of

5(62 signal................................................................................335

Figure 14.6 Writing to TCNT and TCSR (WDT_0) ...................................................................336

Figure 14.7 Conflict between TCNT Write and Increment.........................................................337

Figure 14.8 Sample Circuit for Resetting System by

5(62 Signal............................................338

Section 15 Serial Communication Interface (SCI and IrDA)

Figure 15.1 Block Diagram of SCI .............................................................................................340

Figure 15.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits)...................................................357

Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode.........................................359

Figure 15.4 Relation between Output Clock and Transmit Data Phase

(Asynchronous Mode)..............................................................................................360

Figure 15.5 Sample SCI Initialization Flowchart........................................................................361

Figure 15.6 Example of SCI Transmit Operation in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit) .....................................................362

Figure 15.7 Sample Serial Transmission Flowchart....................................................................363

Figure 15.8 Example of SCI Receive Operation in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit) .....................................................364

Figure 15.9 Sample Serial Reception Flowchart (1) ...................................................................366

Figure 15.9 Sample Serial Reception Flowchart (2) ...................................................................367

HD64F2145 датащи(PDF) 28 Page - Renesas Technology Corp

HD64F2145 датащи(HTML) 28 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL